[PATCH 102/123] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Chris Wilson]

Having completed a test run of gem_eio across all machines in CI we also
observe the phenomenon (of lost interrupts after resetting the GPU) on
gen3 machines as well as the previously sighted gen6/gen7. Let's apply
the same HWSTAM workaround that was effective for gen6+ for all, as
although we haven't seen the same failure on gen4/5 it seems prudent to
keep the code the same.

As a consequence we can remove the extra setting of HWSTAM and apply the
register from a single site.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_irq.c         |  9 ---------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++++++----
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e133fa18cbca..c7c5ca3e6ebb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2885,9 +2885,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (IS_GEN5(dev_priv))
-		I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET(DE);
 	if (IS_GEN7(dev_priv))
 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -3657,8 +3654,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE16(HWSTAM, 0xffff);
-
 	GEN2_IRQ_RESET();
 }
 
@@ -3826,8 +3821,6 @@ static void i915_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
@@ -3937,8 +3930,6 @@ static void i965_irq_reset(struct drm_device *dev)
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
-	I915_WRITE(HWSTAM, 0xffffffff);
-
 	GEN3_IRQ_RESET();
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index daf983b39ea3..d7dec936ff2f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -392,17 +392,25 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		mmio = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (1) {
+		i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
 		u32 mask = ~0u;
 
 		/*
 		 * Keep the render interrupt unmasked as this papers over
 		 * lost interrupts following a reset.
 		 */
-		if (engine->id == RCS)
-			mask &= ~BIT(0);
+		if (engine->id == RCS) {
+			if (INTEL_GEN(dev_priv) >= 6)
+				mask &= ~BIT(0);
+			else
+				mask &= ~I915_USER_INTERRUPT;
+		}
 
-		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
+		if (INTEL_GEN(dev_priv) >= 3)
+			I915_WRITE(hwstam, mask);
+		else
+			I915_WRITE16(hwstam, mask);
 	}
 
 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
-- 
2.19.1