[PATCH 19/20] debug msgs

José Roberto de Souza jose.souza at intel.com
Fri Oct 12 00:46:00 UTC 2018


squash debug

squash debug msg

debug

squash debug

debug
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 31 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c         | 39 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_gem.c         |  2 ++
 drivers/gpu/drm/i915/i915_pci.c         |  2 ++
 drivers/gpu/drm/i915/intel_fbdev.c      |  2 ++
 drivers/gpu/drm/i915/intel_pm.c         |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++-
 7 files changed, 89 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7864bf233d99..7275a621575d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2885,6 +2885,36 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_power_domain_hw(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	int i;
+
+	intel_runtime_pm_get(dev_priv);
+
+	mutex_lock(&power_domains->lock);
+	for (i = 0; i < power_domains->power_well_count; i++) {
+		struct i915_power_well *power_well;
+		bool enabled;
+
+		power_well = &power_domains->power_wells[i];
+		enabled = power_well->desc->ops->is_enabled(dev_priv,
+							    power_well);
+		seq_printf(m, "%-25s hw enabled:%s\n", power_well->desc->name,
+			   yesno(enabled));
+	}
+
+	seq_printf(m, "\tdev_priv->drm.dev->power.usage_count=%d\n", atomic_read(&dev_priv->drm.dev->power.usage_count));
+	seq_printf(m, "\tdev_priv->runtime_pm.wakeref_count=%d\n", atomic_read(&dev_priv->runtime_pm.wakeref_count));
+
+	mutex_unlock(&power_domains->lock);
+
+	intel_runtime_pm_put(dev_priv);
+
+	return 0;
+}
+
 static int i915_power_domain_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4858,6 +4888,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_energy_uJ", i915_energy_uJ, 0},
 	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
 	{"i915_power_domain_info", i915_power_domain_info, 0},
+	{"i915_power_domain_hw", i915_power_domain_hw, 0},
 	{"i915_dmc_info", i915_dmc_info, 0},
 	{"i915_display_info", i915_display_info, 0},
 	{"i915_engine_info", i915_engine_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9d2f51ae3f99..ede86f72c8fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1665,6 +1665,28 @@ static void i915_driver_destroy(struct drm_i915_private *i915)
 	pci_set_drvdata(pdev, NULL);
 }
 
+void power_well_debug(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_well *power_well;
+	bool enabled;
+
+	intel_runtime_pm_get(dev_priv);
+
+	DRM_DEBUG_KMS("power_well_debug {\n");
+	mutex_lock(&dev_priv->power_domains.lock);
+	for_each_power_well(dev_priv, power_well) {
+		enabled = power_well->desc->ops->is_enabled(dev_priv, power_well);
+		DRM_DEBUG_KMS("\t%-23s count=%d hw=%d\n", power_well->desc->name, power_well->count, enabled);
+	}
+
+	DRM_DEBUG_KMS("\tdev_priv->drm.dev->power.usage_count=%d\n", atomic_read(&dev_priv->drm.dev->power.usage_count));
+	DRM_DEBUG_KMS("\tdev_priv->runtime_pm.wakeref_count=%d\n", atomic_read(&dev_priv->runtime_pm.wakeref_count));
+	mutex_unlock(&dev_priv->power_domains.lock);
+	DRM_DEBUG_KMS("}\n");
+
+	intel_runtime_pm_put(dev_priv);
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @pdev: PCI device
@@ -1738,6 +1760,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	i915_welcome_messages(dev_priv);
 
+	power_well_debug(dev_priv);
+
 	return 0;
 
 cleanup_gem:
@@ -2445,6 +2469,8 @@ static int i915_pm_prepare(struct device *kdev)
 	struct pci_dev *pdev = to_pci_dev(kdev);
 	struct drm_device *dev = pci_get_drvdata(pdev);
 
+	DRM_DEBUG_KMS("i915_pm_prepare\n");
+
 	if (!dev) {
 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
 		return -ENODEV;
@@ -2461,6 +2487,8 @@ static int i915_pm_suspend(struct device *kdev)
 	struct pci_dev *pdev = to_pci_dev(kdev);
 	struct drm_device *dev = pci_get_drvdata(pdev);
 
+	DRM_DEBUG_KMS("i915_pm_suspend\n");
+
 	if (!dev) {
 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
 		return -ENODEV;
@@ -2476,6 +2504,8 @@ static int i915_pm_suspend_late(struct device *kdev)
 {
 	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
 
+	DRM_DEBUG_KMS("i915_pm_suspend_late\n");
+
 	/*
 	 * We have a suspend ordering issue with the snd-hda driver also
 	 * requiring our device to be power up. Due to the lack of a
@@ -2495,6 +2525,8 @@ static int i915_pm_poweroff_late(struct device *kdev)
 {
 	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
 
+	DRM_DEBUG_KMS("i915_pm_resume_early\n");
+
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
@@ -2505,6 +2537,8 @@ static int i915_pm_resume_early(struct device *kdev)
 {
 	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
 
+	DRM_DEBUG_KMS("i915_pm_resume\n");
+
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
@@ -2948,6 +2982,8 @@ static int intel_runtime_suspend(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
+	DRM_DEBUG_KMS("i915_runtime_suspend\n");
+
 	if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
 		return -ENODEV;
 
@@ -3044,10 +3080,13 @@ static int intel_runtime_resume(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret = 0;
 
+	DRM_DEBUG_KMS("i915_runtime_resume\n");
+
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
 	DRM_DEBUG_KMS("Resuming device\n");
+	power_well_debug(dev_priv);
 
 	WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
 	disable_rpm_wakeref_asserts(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7d45e71100bc..18c94bcbc20c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3088,6 +3088,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
 	 */
 	intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
 
+	DRM_DEBUG_KMS("engine name=%s\n", engine->name);
+
 	request = engine->reset.prepare(engine);
 	if (request && request->fence.error == -EIO)
 		request = ERR_PTR(-EIO); /* Previous reset failed! */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0a05cc7ace14..7eb9ea6bea54 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -680,6 +680,8 @@ static void i915_pci_remove(struct pci_dev *pdev)
 {
 	struct drm_device *dev;
 
+	DRM_DEBUG_KMS("i915_pci_remove\n");
+
 	dev = pci_get_drvdata(pdev);
 	if (!dev) /* driver load aborted, nothing to cleanup */
 		return;
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 5eaf1c35332b..d187be71b2f0 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -186,6 +186,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
 	void __iomem *vaddr;
 	int ret;
 
+	WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
 	if (intel_fb &&
 	    (sizes->fb_width > intel_fb->base.width ||
 	     sizes->fb_height > intel_fb->base.height)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 838aaf2c719c..7d09d3459da4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9346,6 +9346,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 	else if (IS_GEN5(dev_priv))
 		i915_ironlake_get_mem_freq(dev_priv);
 
+	// this stuff makes sense here?
 	/* For FIFO watermark updates */
 	if (INTEL_GEN(dev_priv) >= 9) {
 		skl_setup_wm_latency(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0f5016b74228..a2e4d530bf34 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -979,7 +979,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 	I915_WRITE(CBR1_VLV, 0);
 
-	WARN_ON(dev_priv->rawclk_freq == 0);
+	WARN_ON(INTEL_INFO(dev_priv)->num_pipes && dev_priv->rawclk_freq == 0);
 
 	I915_WRITE(RAWCLK_FREQ_VLV,
 		   DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
@@ -990,6 +990,10 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 	struct intel_encoder *encoder;
 	enum pipe pipe;
 
+	// TODO no need to run that
+
+	WARN_ON(!INTEL_INFO(dev_priv)->num_pipes);
+
 	/*
 	 * Enable the CRI clock source so we can get at the
 	 * display and the reference clock for VGA
@@ -1587,6 +1591,8 @@ bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 	if (!intel_runtime_pm_get_if_in_use(dev_priv))
 		return false;
 
+	DRM_DEBUG_KMS("intel_display_power_get_if_enabled() domain=%d\n", domain);
+
 	mutex_lock(&power_domains->lock);
 
 	if (__intel_display_power_is_enabled(dev_priv, domain)) {
@@ -3151,11 +3157,16 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
 
+	DRM_DEBUG_KMS("intel_power_domains_sync_hw\n");
+
 	mutex_lock(&power_domains->lock);
 	for_each_power_well(dev_priv, power_well) {
 		power_well->desc->ops->sync_hw(dev_priv, power_well);
 		power_well->hw_enabled =
 			power_well->desc->ops->is_enabled(dev_priv, power_well);
+		if (power_well->hw_enabled) {
+			DRM_DEBUG_KMS("\tpw %s hw enabled\n", power_well->desc->name);
+		}
 	}
 	mutex_unlock(&power_domains->lock);
 }
-- 
2.19.1



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