[PATCH] drm/i915/icl: Use generic name for tc port pll.
Vandita Kulkarni
vandita.kulkarni at intel.com
Mon Oct 22 08:17:52 UTC 2018
MG PLL is a specific type of pll used for TC ports
using MG phy, to have a generic name rename all
MG PLL to TC PLL.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 ++++-----
drivers/gpu/drm/i915/intel_ddi.c | 8 +-
drivers/gpu/drm/i915/intel_display.c | 22 ++---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 164 +++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dpll_mgr.h | 42 ++++-----
5 files changed, 140 insertions(+), 136 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5b37d5f..8ada1eb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3342,26 +3342,26 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);
- seq_printf(m, " mg_refclkin_ctl: 0x%08x\n",
- pll->state.hw_state.mg_refclkin_ctl);
- seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
- pll->state.hw_state.mg_clktop2_coreclkctl1);
- seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n",
- pll->state.hw_state.mg_clktop2_hsclkctl);
- seq_printf(m, " mg_pll_div0: 0x%08x\n",
- pll->state.hw_state.mg_pll_div0);
- seq_printf(m, " mg_pll_div1: 0x%08x\n",
- pll->state.hw_state.mg_pll_div1);
- seq_printf(m, " mg_pll_lf: 0x%08x\n",
- pll->state.hw_state.mg_pll_lf);
- seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
- pll->state.hw_state.mg_pll_frac_lock);
- seq_printf(m, " mg_pll_ssc: 0x%08x\n",
- pll->state.hw_state.mg_pll_ssc);
- seq_printf(m, " mg_pll_bias: 0x%08x\n",
- pll->state.hw_state.mg_pll_bias);
- seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
- pll->state.hw_state.mg_pll_tdc_coldst_bias);
+ seq_printf(m, " tc_refclkin_ctl: 0x%08x\n",
+ pll->state.hw_state.tc_refclkin_ctl);
+ seq_printf(m, " tc_clktop2_coreclkctl1: 0x%08x\n",
+ pll->state.hw_state.tc_clktop2_coreclkctl1);
+ seq_printf(m, " tc_clktop2_hsclkctl: 0x%08x\n",
+ pll->state.hw_state.tc_clktop2_hsclkctl);
+ seq_printf(m, " tc_pll_div0: 0x%08x\n",
+ pll->state.hw_state.tc_pll_div0);
+ seq_printf(m, " tc_pll_div1: 0x%08x\n",
+ pll->state.hw_state.tc_pll_div1);
+ seq_printf(m, " tc_pll_lf: 0x%08x\n",
+ pll->state.hw_state.tc_pll_lf);
+ seq_printf(m, " tc_pll_frac_lock: 0x%08x\n",
+ pll->state.hw_state.tc_pll_frac_lock);
+ seq_printf(m, " tc_pll_ssc: 0x%08x\n",
+ pll->state.hw_state.tc_pll_ssc);
+ seq_printf(m, " tc_pll_bias: 0x%08x\n",
+ pll->state.hw_state.tc_pll_bias);
+ seq_printf(m, " tc_pll_tdc_coldst_bias: 0x%08x\n",
+ pll->state.hw_state.tc_pll_tdc_coldst_bias);
}
drm_modeset_unlock_all(dev);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6b9742b..e39a583 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1087,10 +1087,10 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
MISSING_CASE(clock);
break;
}
- case DPLL_ID_ICL_MGPLL1:
- case DPLL_ID_ICL_MGPLL2:
- case DPLL_ID_ICL_MGPLL3:
- case DPLL_ID_ICL_MGPLL4:
+ case DPLL_ID_ICL_TCPLL1:
+ case DPLL_ID_ICL_TCPLL2:
+ case DPLL_ID_ICL_TCPLL3:
+ case DPLL_ID_ICL_TCPLL4:
return DDI_CLK_SEL_MG;
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc7e3b0..1ce6d81 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9299,7 +9299,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
if (WARN_ON(!intel_dpll_is_combophy(id)))
return;
} else if (intel_port_is_tc(dev_priv, port)) {
- id = icl_port_to_mg_pll_id(port);
+ id = icl_port_to_tc_pll_id(port);
} else {
WARN(1, "Invalid port %x\n", port);
return;
@@ -11676,16 +11676,16 @@ static void __printf(3, 4)
PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_refclkin_ctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_clktop2_coreclkctl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_clktop2_hsclkctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_div0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_div1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_lf);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_frac_lock);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_ssc);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_bias);
+ PIPE_CONF_CHECK_X(dpll_hw_state.tc_pll_tdc_coldst_bias);
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7bdff5b..3666350 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2616,14 +2616,14 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
return link_clock;
}
-static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
+static enum port icl_tc_pll_id_to_port(enum intel_dpll_id id)
{
- return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
+ return id - DPLL_ID_ICL_TCPLL1 + PORT_C;
}
-enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
+enum intel_dpll_id icl_port_to_tc_pll_id(enum port port)
{
- return port - PORT_C + DPLL_ID_ICL_MGPLL1;
+ return port - PORT_C + DPLL_ID_ICL_TCPLL1;
}
bool intel_dpll_is_combophy(enum intel_dpll_id id)
@@ -2631,7 +2631,7 @@ bool intel_dpll_is_combophy(enum intel_dpll_id id)
return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
}
-static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
+static bool icl_tc_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
uint32_t *target_dco_khz,
struct intel_dpll_hw_state *state)
{
@@ -2683,12 +2683,12 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
*target_dco_khz = dco;
- state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
+ state->tc_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
- state->mg_clktop2_coreclkctl1 =
+ state->tc_clktop2_coreclkctl1 =
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
- state->mg_clktop2_hsclkctl =
+ state->tc_clktop2_hsclkctl =
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
hsdiv |
@@ -2705,7 +2705,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
* The specification for this function uses real numbers, so the math had to be
* adapted to integer-only calculation, that's why it looks so different.
*/
-static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
+static bool icl_calc_tc_pll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder, int clock,
struct intel_dpll_hw_state *pll_state)
{
@@ -2720,7 +2720,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
bool use_ssc = false;
bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
- if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
+ if (!icl_tc_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
pll_state)) {
DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
return false;
@@ -2810,43 +2810,43 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
ssc_steplog = 4;
- pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
+ pll_state->tc_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
MG_PLL_DIV0_FBDIV_INT(m2div_int);
- pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
+ pll_state->tc_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
MG_PLL_DIV1_DITHER_DIV_2 |
MG_PLL_DIV1_NDIVRATIO(1) |
MG_PLL_DIV1_FBPREDIV(m1div);
- pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
+ pll_state->tc_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
MG_PLL_LF_AFCCNTSEL_512 |
MG_PLL_LF_GAINCTRL(1) |
MG_PLL_LF_INT_COEFF(int_coeff) |
MG_PLL_LF_PROP_COEFF(prop_coeff);
- pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
+ pll_state->tc_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
MG_PLL_FRAC_LOCK_DCODITHEREN |
MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
if (use_ssc || m2div_rem > 0)
- pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
+ pll_state->tc_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
- pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
+ pll_state->tc_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
MG_PLL_SSC_TYPE(2) |
MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
MG_PLL_SSC_STEPNUM(ssc_steplog) |
MG_PLL_SSC_FLLEN |
MG_PLL_SSC_STEPSIZE(ssc_stepsize);
- pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
+ pll_state->tc_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
MG_PLL_TDC_COLDST_IREFINT_EN |
MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
MG_PLL_TDC_TDCOVCCORR_EN |
MG_PLL_TDC_TDCSEL(3);
- pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
+ pll_state->tc_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
MG_PLL_BIAS_BIAS_BONUS(10) |
MG_PLL_BIAS_BIASCAL_EN |
@@ -2855,15 +2855,17 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
MG_PLL_BIAS_IREFTRIM(iref_trim);
if (refclk_khz == 38400) {
- pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
- pll_state->mg_pll_bias_mask = 0;
+ pll_state->tc_pll_tdc_coldst_bias_mask =
+ MG_PLL_TDC_COLDST_COLDSTART;
+ pll_state->tc_pll_bias_mask = 0;
} else {
- pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
- pll_state->mg_pll_bias_mask = -1U;
+ pll_state->tc_pll_tdc_coldst_bias_mask = -1U;
+ pll_state->tc_pll_bias_mask = -1U;
}
- pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
- pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+ pll_state->tc_pll_tdc_coldst_bias &=
+ pll_state->tc_pll_tdc_coldst_bias_mask;
+ pll_state->tc_pll_bias &= pll_state->tc_pll_bias_mask;
return true;
}
@@ -2894,9 +2896,9 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
ret = icl_calc_dpll_state(crtc_state, encoder, clock,
&pll_state);
} else {
- min = icl_port_to_mg_pll_id(port);
+ min = icl_port_to_tc_pll_id(port);
max = min;
- ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
+ ret = icl_calc_tc_pll_state(crtc_state, encoder, clock,
&pll_state);
}
} else {
@@ -2933,7 +2935,7 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
* TODO: Make MG_PLL macros use
* tc port id instead of port id
*/
- return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
+ return MG_PLL_ENABLE(icl_tc_pll_id_to_port(id));
}
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -2957,43 +2959,45 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
} else {
- port = icl_mg_pll_id_to_port(id);
- hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
- hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+ port = icl_tc_pll_id_to_port(id);
+ hw_state->tc_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
+ hw_state->tc_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
- hw_state->mg_clktop2_coreclkctl1 =
+ hw_state->tc_clktop2_coreclkctl1 =
I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
- hw_state->mg_clktop2_coreclkctl1 &=
+ hw_state->tc_clktop2_coreclkctl1 &=
MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
- hw_state->mg_clktop2_hsclkctl =
+ hw_state->tc_clktop2_hsclkctl =
I915_READ(MG_CLKTOP2_HSCLKCTL(port));
- hw_state->mg_clktop2_hsclkctl &=
+ hw_state->tc_clktop2_hsclkctl &=
MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
- hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
- hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));
- hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
- hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
- hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
+ hw_state->tc_pll_div0 = I915_READ(MG_PLL_DIV0(port));
+ hw_state->tc_pll_div1 = I915_READ(MG_PLL_DIV1(port));
+ hw_state->tc_pll_lf = I915_READ(MG_PLL_LF(port));
+ hw_state->tc_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
+ hw_state->tc_pll_ssc = I915_READ(MG_PLL_SSC(port));
- hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
- hw_state->mg_pll_tdc_coldst_bias =
+ hw_state->tc_pll_bias = I915_READ(MG_PLL_BIAS(port));
+ hw_state->tc_pll_tdc_coldst_bias =
I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
if (dev_priv->cdclk.hw.ref == 38400) {
- hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
- hw_state->mg_pll_bias_mask = 0;
+ hw_state->tc_pll_tdc_coldst_bias_mask =
+ MG_PLL_TDC_COLDST_COLDSTART;
+ hw_state->tc_pll_bias_mask = 0;
} else {
- hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
- hw_state->mg_pll_bias_mask = -1U;
+ hw_state->tc_pll_tdc_coldst_bias_mask = -1U;
+ hw_state->tc_pll_bias_mask = -1U;
}
- hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
- hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
+ hw_state->tc_pll_tdc_coldst_bias &=
+ hw_state->tc_pll_tdc_coldst_bias_mask;
+ hw_state->tc_pll_bias &= hw_state->tc_pll_bias_mask;
}
ret = true;
@@ -3017,23 +3021,23 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
- enum port port = icl_mg_pll_id_to_port(pll->info->id);
+ enum port port = icl_tc_pll_id_to_port(pll->info->id);
u32 val;
/*
* Some of the following registers have reserved fields, so program
* these with RMW based on a mask. The mask can be fixed or generated
* during the calc/readout phase if the mask depends on some other HW
- * state like refclk, see icl_calc_mg_pll_state().
+ * state like refclk, see icl_calc_tc_pll_state().
*/
val = I915_READ(MG_REFCLKIN_CTL(port));
val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
- val |= hw_state->mg_refclkin_ctl;
+ val |= hw_state->tc_refclkin_ctl;
I915_WRITE(MG_REFCLKIN_CTL(port), val);
val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
- val |= hw_state->mg_clktop2_coreclkctl1;
+ val |= hw_state->tc_clktop2_coreclkctl1;
I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port), val);
val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
@@ -3041,23 +3045,23 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
- val |= hw_state->mg_clktop2_hsclkctl;
+ val |= hw_state->tc_clktop2_hsclkctl;
I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), val);
- I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0);
- I915_WRITE(MG_PLL_DIV1(port), hw_state->mg_pll_div1);
- I915_WRITE(MG_PLL_LF(port), hw_state->mg_pll_lf);
- I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->mg_pll_frac_lock);
- I915_WRITE(MG_PLL_SSC(port), hw_state->mg_pll_ssc);
+ I915_WRITE(MG_PLL_DIV0(port), hw_state->tc_pll_div0);
+ I915_WRITE(MG_PLL_DIV1(port), hw_state->tc_pll_div1);
+ I915_WRITE(MG_PLL_LF(port), hw_state->tc_pll_lf);
+ I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->tc_pll_frac_lock);
+ I915_WRITE(MG_PLL_SSC(port), hw_state->tc_pll_ssc);
val = I915_READ(MG_PLL_BIAS(port));
- val &= ~hw_state->mg_pll_bias_mask;
- val |= hw_state->mg_pll_bias;
+ val &= ~hw_state->tc_pll_bias_mask;
+ val |= hw_state->tc_pll_bias;
I915_WRITE(MG_PLL_BIAS(port), val);
val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
- val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
- val |= hw_state->mg_pll_tdc_coldst_bias;
+ val &= ~hw_state->tc_pll_tdc_coldst_bias_mask;
+ val |= hw_state->tc_pll_tdc_coldst_bias;
I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port), val);
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));
@@ -3146,22 +3150,22 @@ static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
struct intel_dpll_hw_state *hw_state)
{
DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
- "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
- "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
- "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
- "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
- "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
+ "tc_refclkin_ctl: 0x%x, tc_clktop2_coreclkctl1: 0x%x, "
+ "tc_clktop2_hsclkctl: 0x%x, tc_pll_div0: 0x%x, "
+ "tc_pll_div2: 0x%x, tc_pll_lf: 0x%x, "
+ "tc_pll_frac_lock: 0x%x, tc_pll_ssc: 0x%x, "
+ "tc_pll_bias: 0x%x, tc_pll_tdc_coldst_bias: 0x%x\n",
hw_state->cfgcr0, hw_state->cfgcr1,
- hw_state->mg_refclkin_ctl,
- hw_state->mg_clktop2_coreclkctl1,
- hw_state->mg_clktop2_hsclkctl,
- hw_state->mg_pll_div0,
- hw_state->mg_pll_div1,
- hw_state->mg_pll_lf,
- hw_state->mg_pll_frac_lock,
- hw_state->mg_pll_ssc,
- hw_state->mg_pll_bias,
- hw_state->mg_pll_tdc_coldst_bias);
+ hw_state->tc_refclkin_ctl,
+ hw_state->tc_clktop2_coreclkctl1,
+ hw_state->tc_clktop2_hsclkctl,
+ hw_state->tc_pll_div0,
+ hw_state->tc_pll_div1,
+ hw_state->tc_pll_lf,
+ hw_state->tc_pll_frac_lock,
+ hw_state->tc_pll_ssc,
+ hw_state->tc_pll_bias,
+ hw_state->tc_pll_tdc_coldst_bias);
}
static const struct intel_shared_dpll_funcs icl_pll_funcs = {
@@ -3174,10 +3178,10 @@ static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
{ "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
{ "TBT PLL", &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
- { "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
- { "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
- { "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
- { "MG PLL 4", &icl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
+ { "TC PLL 1", &icl_pll_funcs, DPLL_ID_ICL_TCPLL1, 0 },
+ { "TC PLL 2", &icl_pll_funcs, DPLL_ID_ICL_TCPLL2, 0 },
+ { "TC PLL 3", &icl_pll_funcs, DPLL_ID_ICL_TCPLL3, 0 },
+ { "TC PLL 4", &icl_pll_funcs, DPLL_ID_ICL_TCPLL4, 0 },
{ },
};
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index a033d8f..b2d6a2b 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -118,21 +118,21 @@ enum intel_dpll_id {
*/
DPLL_ID_ICL_TBTPLL = 2,
/**
- * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+ * @DPLL_ID_ICL_TCPLL1: ICL TC PLL 1 port 1 (C)
*/
- DPLL_ID_ICL_MGPLL1 = 3,
+ DPLL_ID_ICL_TCPLL1 = 3,
/**
- * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+ * @DPLL_ID_ICL_TCPLL2: ICL TC PLL 1 port 2 (D)
*/
- DPLL_ID_ICL_MGPLL2 = 4,
+ DPLL_ID_ICL_TCPLL2 = 4,
/**
- * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+ * @DPLL_ID_ICL_TCPLL3: ICL TC PLL 1 port 3 (E)
*/
- DPLL_ID_ICL_MGPLL3 = 5,
+ DPLL_ID_ICL_TCPLL3 = 5,
/**
- * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+ * @DPLL_ID_ICL_TCPLL4: ICL TC PLL 1 port 4 (F)
*/
- DPLL_ID_ICL_MGPLL4 = 6,
+ DPLL_ID_ICL_TCPLL4 = 6,
};
#define I915_NUM_PLLS 7
@@ -170,18 +170,18 @@ struct intel_dpll_hw_state {
* ICL uses the following, already defined:
* uint32_t cfgcr0, cfgcr1;
*/
- uint32_t mg_refclkin_ctl;
- uint32_t mg_clktop2_coreclkctl1;
- uint32_t mg_clktop2_hsclkctl;
- uint32_t mg_pll_div0;
- uint32_t mg_pll_div1;
- uint32_t mg_pll_lf;
- uint32_t mg_pll_frac_lock;
- uint32_t mg_pll_ssc;
- uint32_t mg_pll_bias;
- uint32_t mg_pll_tdc_coldst_bias;
- uint32_t mg_pll_bias_mask;
- uint32_t mg_pll_tdc_coldst_bias_mask;
+ uint32_t tc_refclkin_ctl;
+ uint32_t tc_clktop2_coreclkctl1;
+ uint32_t tc_clktop2_hsclkctl;
+ uint32_t tc_pll_div0;
+ uint32_t tc_pll_div1;
+ uint32_t tc_pll_lf;
+ uint32_t tc_pll_frac_lock;
+ uint32_t tc_pll_ssc;
+ uint32_t tc_pll_bias;
+ uint32_t tc_pll_tdc_coldst_bias;
+ uint32_t tc_pll_bias_mask;
+ uint32_t tc_pll_tdc_coldst_bias_mask;
};
/**
@@ -345,7 +345,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
uint32_t pll_id);
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
-enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
+enum intel_dpll_id icl_port_to_tc_pll_id(enum port port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
#endif /* _INTEL_DPLL_MGR_H_ */
--
1.9.1
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