[PATCH 01/10] drm/i915/execlists: Move RPCS setup to context pin

[Chris Wilson]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Configuring RPCS in context image just before pin is sufficient and will
come extra handy in one of the following patches.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Suggested-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index def467c2451b..7ee53f125551 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1303,6 +1303,8 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
 	return i915_vma_pin(vma, 0, 0, flags);
 }
 
+static u32 make_rpcs(struct drm_i915_private *dev_priv);
+
 static struct intel_context *
 __execlists_context_pin(struct intel_engine_cs *engine,
 			struct i915_gem_context *ctx,
@@ -1338,6 +1340,11 @@ __execlists_context_pin(struct intel_engine_cs *engine,
 	GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
 	ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
 
+	/* RPCS */
+	ce->lrc_reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
+	CTX_REG(ce->lrc_reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+		make_rpcs(engine->i915));
+
 	ce->state->obj->pin_global++;
 	i915_gem_context_get(ctx);
 	return ce;
@@ -2696,13 +2703,8 @@ static void execlists_init_reg_state(u32 *regs,
 		ASSIGN_CTX_PML4(ppgtt, regs);
 	}
 
-	if (rcs) {
-		regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
-		CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
-			make_rpcs(dev_priv));
-
+	if (rcs)
 		i915_oa_init_reg_state(engine, ctx, regs);
-	}
 
 	regs[CTX_END] = MI_BATCH_BUFFER_END;
 	if (INTEL_GEN(dev_priv) >= 10)
-- 
2.19.0.rc1