[PATCH 08/10] ce-active

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_gem_context.c | 41 +++++++++++--------------
 drivers/gpu/drm/i915/i915_gem_context.h |  2 ++
 2 files changed, 20 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b1e0c008bfa0..2f2e4b2509c4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -265,6 +265,14 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	return desc;
 }
 
+static void intel_context_retire(struct i915_gem_active *active,
+				 struct i915_request *rq)
+{
+	struct intel_context *ce = container_of(active, typeof(*ce), active);
+
+	intel_context_unpin(ce);
+}
+
 static struct i915_gem_context *
 __create_hw_context(struct drm_i915_private *dev_priv,
 		    struct drm_i915_file_private *file_priv)
@@ -294,6 +302,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 		ce->gem_context = ctx;
 		/* Use the whole device by default */
 		ce->sseu = intel_device_default_sseu(dev_priv);
+
+		init_request_active(&ce->active, intel_context_retire);
 	}
 
 	INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
@@ -874,42 +884,21 @@ static int gen8_emit_rpcs_config(struct i915_request *rq,
 				 struct intel_context *ce,
 				 struct intel_sseu sseu)
 {
-	struct drm_i915_private *i915 = rq->i915;
-	struct i915_vma *vma;
 	u64 offset;
 	u32 *cs;
-	int err;
-
-	vma = i915_vma_instance(ce->state->obj, &i915->ggtt.vm, NULL);
-	if (IS_ERR(vma))
-		return PTR_ERR(vma);
-
-	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
-	if (err) {
-		i915_vma_close(vma);
-		return err;
-	}
-
-	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
-	if (unlikely(err)) {
-		i915_vma_close(vma);
-		return err;
-	}
-
-	i915_vma_unpin(vma);
 
 	cs = intel_ring_begin(rq, 4);
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	offset = vma->node.start +
+	offset = ce->state->node.start +
 		LRC_STATE_PN * PAGE_SIZE +
 		(CTX_R_PWR_CLK_STATE + 1) * 4;
 
 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
 	*cs++ = lower_32_bits(offset);
 	*cs++ = upper_32_bits(offset);
-	*cs++ = gen8_make_rpcs(i915, &sseu);
+	*cs++ = gen8_make_rpcs(rq->i915, &sseu);
 
 	intel_ring_advance(rq, cs);
 
@@ -930,6 +919,8 @@ gen8_modify_rpcs_gpu(struct intel_context *ce,
 	/* Submitting requests etc needs the hw awake. */
 	intel_runtime_pm_get(i915);
 
+	__intel_context_pin(ce);
+
 	rq = i915_request_alloc(engine, i915->kernel_context);
 	if (IS_ERR(rq)) {
 		ret = PTR_ERR(rq);
@@ -951,6 +942,10 @@ gen8_modify_rpcs_gpu(struct intel_context *ce,
 	/* Order all following requests to be after. */
 	i915_timeline_set_barrier(ce->ring->timeline, rq);
 
+	if (i915_gem_active_isset(&ce->active))
+		intel_context_unpin(ce);
+	i915_gem_active_set(&ce->active, rq);
+
 out_add:
 	i915_request_add(rq);
 out_put:
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index 1e51c2a46644..a9662d7c7ad4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -157,6 +157,8 @@ struct i915_gem_context {
 		u64 lrc_desc;
 		int pin_count;
 
+		struct i915_gem_active active;
+
 		const struct intel_context_ops *ops;
 
 		/** sseu: Control eu/slice partitioning */
-- 
2.19.0.rc1