[PATCH 05/10] drm/i915: make GEN6 intel GPU series configurable

Andi Shyti andi.shyti at intel.com
Wed Sep 12 13:18:16 UTC 2018


GEN6 consists of

  Sandy Bridge

GPU.

Signed-off-by: Andi Shyti <andi.shyti at intel.com>
---
 drivers/gpu/drm/i915/Kconfig.sel | 13 +++++++++++++
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/i915_pci.c  |  6 ++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
index 8ec0312787ae..fca3efd80fa3 100644
--- a/drivers/gpu/drm/i915/Kconfig.sel
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -137,3 +137,16 @@ config DRM_INTEL_IRONLAKE
 	select DRM_INTEL_GEN5
 	help
 	  Choose this option if you have an Iron Lake gpu
+
+comment "Intel GEN6"
+
+config DRM_INTEL_GEN6
+	bool
+
+config DRM_INTEL_SANDYBRIDGE
+	bool "Intel Sandy Bridge GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN6
+	help
+	  Choose this option if you have a Sandy Bridge gpu
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 230766e98afd..3637e0ab2268 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2523,7 +2523,6 @@ intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
 #define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
@@ -2536,6 +2535,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN3(dev_priv)	__IS_GEN_X(3, dev_priv)
 #define IS_GEN4(dev_priv)	__IS_GEN_X(4, dev_priv)
 #define IS_GEN5(dev_priv)	__IS_GEN_X(5, dev_priv)
+#define IS_GEN6(dev_priv)	__IS_GEN_X(6, dev_priv)
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 55678422896f..c169de9fcf72 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -278,6 +278,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 };
 #endif
 
+#ifdef CONFIG_DRM_INTEL_GEN6
 #define GEN6_FEATURES \
 	GEN(6), \
 	.num_pipes = 2, \
@@ -292,7 +293,9 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 #define SNB_D_PLATFORM \
 	GEN6_FEATURES, \
 	PLATFORM(INTEL_SANDYBRIDGE)
@@ -322,6 +325,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	SNB_M_PLATFORM,
 	.gt = 2,
 };
+#endif
 
 #define GEN7_FEATURES  \
 	GEN(7), \
@@ -701,10 +705,12 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
+#endif
 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
-- 
2.19.0



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