[PATCH 02/10] drm/i915: make GEN3 intel GPU series configurable
Andi Shyti
andi.shyti at intel.com
Wed Sep 12 13:18:13 UTC 2018
GEN3 consists of:
i915g
i915gm
i9145g
i9145gm
g33
pineview
GPUs
Signed-off-by: Andi Shyti <andi.shyti at intel.com>
---
drivers/gpu/drm/i915/Kconfig | 3 +-
drivers/gpu/drm/i915/Kconfig.sel | 53 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 18 +++++------
drivers/gpu/drm/i915/i915_pci.c | 26 ++++++++++++++++
4 files changed, 89 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 002a63b9a701..e82551d71177 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -28,8 +28,7 @@ config DRM_I915
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
- including 915G, 945G, 965G,
- G35, G41, G43, G45 chipsets and Celeron, Pentium, Core i3,
+ including 965G, G41, G43, G45 chipsets and Celeron, Pentium, Core i3,
Core i5, Core i7 as well as Atom CPUs with integrated graphics.
This driver is used by the Intel driver in X.org 6.8 and
diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
index fc1709979d21..e2450a6844c6 100644
--- a/drivers/gpu/drm/i915/Kconfig.sel
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -34,3 +34,56 @@ config DRM_INTEL_I865G
select DRM_INTEL_GEN2
help
Choose this option if you have an i865G gpu
+
+comment "Intel GEN3"
+
+config DRM_INTEL_GEN3
+ bool
+
+config DRM_INTEL_I915G
+ bool "Intel i915G GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN3
+ help
+ Choose this option if you have an i915G gpu
+
+config DRM_INTEL_I915GM
+ bool "Intel i915GM GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN3
+ help
+ Choose this option if you have an i915GM gpu
+
+config DRM_INTEL_I945G
+ bool "Intel i945G GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN3
+ help
+ Choose this option if you have an i945G gpu
+
+config DRM_INTEL_I945GM
+ bool "Intel i945GM GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN3
+ help
+ Choose this option if you have an i945GM gpu
+
+config DRM_INTEL_G33
+ bool "Intel G33 GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN3
+ help
+ Choose this option if you have an G33 gpu
+
+config DRM_INTEL_PINEVIEW
+ bool "Intel Pine View GPU"
+ default y
+ depends on DRM_I915
+ select DRM_INTEL_GEN3
+ help
+ Choose this option if you have an Pine View gpu
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 36356bd2efd4..05eabcf2b454 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2379,19 +2379,19 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_I845G(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I865G)
-#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
-#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
-#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
-#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
+#define IS_I915G(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I915G)
+#define IS_I915GM(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I915GM)
+#define IS_I945G(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I945G)
+#define IS_I945GM(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
-#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
-#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
+#define IS_PINEVIEW_G(dev_priv) IS_SELECTED_ID(dev_priv, INTEL_PINEVIEW, 0xa001)
+#define IS_PINEVIEW_M(dev_priv) IS_SELECTED_ID(dev_priv, INTEL_PINEVIEW, 0xa011)
+#define IS_PINEVIEW(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_PINEVIEW)
+#define IS_G33(dev_priv) IS_SELECTED_PLATFORM(dev_priv, INTEL_G33)
#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
@@ -2520,7 +2520,6 @@ intel_info(const struct drm_i915_private *dev_priv)
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
@@ -2533,6 +2532,7 @@ intel_info(const struct drm_i915_private *dev_priv)
!!((dev_priv)->info.gen_mask & BIT(N-1)))
#define IS_GEN2(dev_priv) __IS_GEN_X(2, dev_priv)
+#define IS_GEN3(dev_priv) __IS_GEN_X(3, dev_priv)
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c2e97aac27c8..f99f3530d13c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -115,6 +115,7 @@ static const struct intel_device_info intel_i865g_info = {
};
#endif
+#ifdef CONFIG_DRM_INTEL_GEN3
#define GEN3_FEATURES \
GEN(3), \
.num_pipes = 2, \
@@ -125,7 +126,9 @@ static const struct intel_device_info intel_i865g_info = {
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
+#endif
+#ifdef CONFIG_DRM_INTEL_I915G
static const struct intel_device_info intel_i915g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915G),
@@ -135,7 +138,9 @@ static const struct intel_device_info intel_i915g_info = {
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_I915GM
static const struct intel_device_info intel_i915gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915GM),
@@ -147,7 +152,9 @@ static const struct intel_device_info intel_i915gm_info = {
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_I945G
static const struct intel_device_info intel_i945g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945G),
@@ -156,7 +163,9 @@ static const struct intel_device_info intel_i945g_info = {
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_I945GM
static const struct intel_device_info intel_i945gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945GM),
@@ -168,14 +177,18 @@ static const struct intel_device_info intel_i945gm_info = {
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_G33
static const struct intel_device_info intel_g33_info = {
GEN3_FEATURES,
PLATFORM(INTEL_G33),
.has_hotplug = 1,
.has_overlay = 1,
};
+#endif
+#ifdef CONFIG_DRM_INTEL_PINEVIEW
static const struct intel_device_info intel_pineview_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
@@ -183,6 +196,7 @@ static const struct intel_device_info intel_pineview_info = {
.has_hotplug = 1,
.has_overlay = 1,
};
+#endif
#define GEN4_FEATURES \
GEN(4), \
@@ -641,16 +655,28 @@ static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_INTEL_I865G
INTEL_I865G_IDS(&intel_i865g_info),
#endif
+#ifdef CONFIG_DRM_INTEL_I915G
INTEL_I915G_IDS(&intel_i915g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I915GM
INTEL_I915GM_IDS(&intel_i915gm_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I945G
INTEL_I945G_IDS(&intel_i945g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I945GM
INTEL_I945GM_IDS(&intel_i945gm_info),
+#endif
INTEL_I965G_IDS(&intel_i965g_info),
+#ifdef CONFIG_DRM_INTEL_G33
INTEL_G33_IDS(&intel_g33_info),
+#endif
INTEL_I965GM_IDS(&intel_i965gm_info),
INTEL_GM45_IDS(&intel_gm45_info),
INTEL_G45_IDS(&intel_g45_info),
+#ifdef CONFIG_DRM_INTEL_PINEVIEW
INTEL_PINEVIEW_IDS(&intel_pineview_info),
+#endif
INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
--
2.19.0
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