[PATCH 2/2] drm/i915: Move display HW state readout to early resume phase

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 139 ++++++++++++++++++++--------------------
 1 file changed, 70 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 643473d8d1d6..255980e4ca32 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1891,7 +1891,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct pci_dev *pdev = dev_priv->drm.pdev;
-	pci_power_t opregion_target_state;
 
 	disable_rpm_wakeref_asserts(dev_priv);
 
@@ -1905,30 +1904,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	intel_display_suspend(dev);
 
-	intel_dp_mst_suspend(dev_priv);
-
-	intel_runtime_pm_disable_interrupts(dev_priv);
-	intel_hpd_cancel_work(dev_priv);
-
-	intel_suspend_encoders(dev_priv);
-
-	intel_suspend_hw(dev_priv);
-
-	i915_gem_suspend_gtt_mappings(dev_priv);
-
-	i915_save_state(dev_priv);
-
-	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
-	intel_opregion_notify_adapter(dev_priv, opregion_target_state);
-
-	intel_opregion_unregister(dev_priv);
-
-	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
-
-	dev_priv->suspend_count++;
-
-	intel_csr_ucode_suspend(dev_priv);
-
 	enable_rpm_wakeref_asserts(dev_priv);
 
 	return 0;
@@ -1950,10 +1925,36 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct pci_dev *pdev = dev_priv->drm.pdev;
+	pci_power_t opregion_target_state;
 	int ret;
 
 	disable_rpm_wakeref_asserts(dev_priv);
 
+	intel_dp_mst_suspend(dev_priv);
+
+	intel_runtime_pm_disable_interrupts(dev_priv);
+	intel_hpd_cancel_work(dev_priv);
+
+	intel_suspend_encoders(dev_priv);
+
+	intel_suspend_hw(dev_priv);
+
+	i915_gem_suspend_gtt_mappings(dev_priv);
+
+	i915_save_state(dev_priv);
+
+	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
+	intel_opregion_notify_adapter(dev_priv, opregion_target_state);
+
+	intel_opregion_unregister(dev_priv);
+
+	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
+
+	dev_priv->suspend_count++;
+
+	intel_csr_ucode_suspend(dev_priv);
+
+
 	i915_gem_suspend_late(dev_priv);
 
 	intel_uncore_suspend(dev_priv);
@@ -2025,52 +2026,8 @@ static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 static int i915_drm_resume(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	int ret;
 
 	disable_rpm_wakeref_asserts(dev_priv);
-	intel_sanitize_gt_powersave(dev_priv);
-
-	i915_gem_sanitize(dev_priv);
-
-	ret = i915_ggtt_enable_hw(dev_priv);
-	if (ret)
-		DRM_ERROR("failed to re-enable GGTT\n");
-
-	intel_csr_ucode_resume(dev_priv);
-
-	i915_restore_state(dev_priv);
-	intel_pps_unlock_regs_wa(dev_priv);
-	intel_opregion_setup(dev_priv);
-
-	intel_init_pch_refclk(dev_priv);
-
-	/*
-	 * Interrupts have to be enabled before any batches are run. If not the
-	 * GPU will hang. i915_gem_init_hw() will initiate batches to
-	 * update/restore the context.
-	 *
-	 * drm_mode_config_reset() needs AUX interrupts.
-	 *
-	 * Modeset enabling in intel_modeset_init_hw() also needs working
-	 * interrupts.
-	 */
-	intel_runtime_pm_enable_interrupts(dev_priv);
-
-	drm_mode_config_reset(dev);
-
-	i915_gem_resume(dev_priv);
-
-	intel_modeset_init_hw(dev);
-	intel_init_clock_gating(dev_priv);
-
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display.hpd_irq_setup)
-		dev_priv->display.hpd_irq_setup(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-
-	intel_dp_mst_resume(dev_priv);
-
-	intel_display_readout_hw_state(dev_priv);
 	intel_display_resume(dev);
 
 	drm_kms_helper_poll_enable(dev);
@@ -2169,6 +2126,50 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	intel_engines_sanitize(dev_priv);
 
+	intel_sanitize_gt_powersave(dev_priv);
+
+	i915_gem_sanitize(dev_priv);
+
+	ret = i915_ggtt_enable_hw(dev_priv);
+	if (ret)
+		DRM_ERROR("failed to re-enable GGTT\n");
+
+	intel_csr_ucode_resume(dev_priv);
+
+	i915_restore_state(dev_priv);
+	intel_pps_unlock_regs_wa(dev_priv);
+	intel_opregion_setup(dev_priv);
+
+	intel_init_pch_refclk(dev_priv);
+
+	/*
+	 * Interrupts have to be enabled before any batches are run. If not the
+	 * GPU will hang. i915_gem_init_hw() will initiate batches to
+	 * update/restore the context.
+	 *
+	 * drm_mode_config_reset() needs AUX interrupts.
+	 *
+	 * Modeset enabling in intel_modeset_init_hw() also needs working
+	 * interrupts.
+	 */
+	intel_runtime_pm_enable_interrupts(dev_priv);
+
+	drm_mode_config_reset(dev);
+
+	i915_gem_resume(dev_priv);
+
+	intel_modeset_init_hw(dev);
+	intel_init_clock_gating(dev_priv);
+
+	spin_lock_irq(&dev_priv->irq_lock);
+	if (dev_priv->display.hpd_irq_setup)
+		dev_priv->display.hpd_irq_setup(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
+	intel_dp_mst_resume(dev_priv);
+
+	intel_display_readout_hw_state(dev_priv);
+
 	enable_rpm_wakeref_asserts(dev_priv);
 
 	return ret;
-- 
2.13.2