✗ Fi.CI.BAT: failure for series starting with [v3,01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming

Patchwork patchwork at emeril.freedesktop.org
Mon Sep 17 19:46:43 UTC 2018 

== Series Details ==

Series: series starting with [v3,01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
URL   : https://patchwork.freedesktop.org/series/49809/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4834 -> Trybot_2931 =

== Summary - FAILURE ==

  Serious unknown changes coming with Trybot_2931 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Trybot_2931, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49809/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Trybot_2931:

  === IGT changes ===

    ==== Possible regressions ====

    igt at debugfs_test@read_all_entries:
      fi-icl-u:           PASS -> DMESG-WARN +1

    igt at drv_selftest@live_contexts:
      fi-bsw-n3050:       PASS -> DMESG-WARN

    igt at gem_close_race@basic-threads:
      fi-byt-j1900:       PASS -> DMESG-WARN

    igt at kms_busy@basic-flip-b:
      fi-icl-u:           PASS -> INCOMPLETE

    
    ==== Warnings ====

    igt at pm_rpm@module-reload:
      fi-hsw-4770r:       SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Trybot_2931 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt at drv_selftest@live_guc:
      fi-skl-guc:         NOTRUN -> DMESG-WARN (fdo#107258)

    igt at gem_exec_suspend@basic-s3:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt at drv_getparams_basic@basic-subslice-total:
      fi-snb-2520m:       DMESG-WARN (fdo#103713) -> PASS +10

    igt at drv_module_reload@basic-reload-inject:
      fi-hsw-4770r:       DMESG-WARN (fdo#107924, fdo#107425) -> PASS

    igt at kms_psr@primary_page_flip:
      fi-kbl-r:           FAIL (fdo#107336) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924


== Participating hosts (47 -> 40) ==

  Additional (1): fi-skl-guc 
  Missing    (8): fi-ilk-m540 fi-skl-gvtdvm fi-hsw-4200u fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


== Build changes ==

    * Linux: CI_DRM_4834 -> Trybot_2931

  CI_DRM_4834: e13c7f93395b309bc440805cb7ee957c63324fa0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4645: 03b90a39ed12a568c9da752466ea708d6348e110 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Trybot_2931: 898f81fe1813f7551a5ee4c8839842e5c3749aca @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

898f81fe1813 drm/i915: Force DSC enable if requested by IGT
0a2a3c6636c6 Per connector DSC Support node
1d97b696a10a drm/i915/dp: Add POWER_INIT to PW2
b0f6aec55b0e drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
2d300fb760c7 drm/i915/dp: Configure Display stream splitter registers during DSC enable
720452fa7ec4 drm/i915/icl: Add Display Stream Splitter control registers
95cd5656431b drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
43eee20ed15b drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
e9c11af1103d drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
07c4dd4e13d6 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
d9da1de01e7a drm/i915/dp: Enable/Disable DSC in DP Sink
4f15d9932472 drm/i915/dsc: Compute Rate Control parameters for DSC
6cc302f90f27 drm/i915/dsc: Define & Compute VESA DSC params
e5448e73ee55 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
06da53d0b865 drm/i915/dp: Do not enable PSR2 if DSC is enabled
c1e300f546a5 drm/i915/dp: Compute DSC pipe config in atomic check
785fe7e0d56c drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
43f79b08ff2a drm/dsc: Add helpers for DSC picture parameter set infoframes
ae3c82a327cb drm/dsc: Define Rate Control values that do not change over configurations
106fc13470cd drm/dsc: Define VESA Display Stream Compression Capabilities
bdc0ba54fabf drm/dsc: Define Display Stream Compression PPS infoframe
1d03b7eabe9d drm/dp: Define payload size for DP SDP PPS packet
5ea084c9d292 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
f7a034423f09 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
aded66b010c8 drm/dp: DRM DP helper/macros to get DP sink DSC parameters
d906c942c276 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
5614a68b484b drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
db72f2c48a3f drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2931/issues.html

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