[PATCH 02/14] drm/i915/psr: Add HBR3 support

[José Roberto de Souza]

As in the regular link trainning, if the sink and source supports
HBR3, TP4 should be used as link pattern training.

Cc: Manasi Navare <manasi.d.navare at intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h               |  7 +++++
 drivers/gpu/drm/i915/intel_dp_link_training.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h              |  1 +
 drivers/gpu/drm/i915/intel_psr.c              | 28 ++++++++++++++-----
 4 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4948b352bf4c..d4343d151056 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4132,6 +4132,7 @@ enum {
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2 << 25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3 << 25)
 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
+#define   EDP_PSR_TP4_SEL			13 /* ICL+ */
 #define   EDP_PSR_SKIP_AUX_EXIT			(1 << 12)
 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
 #define   EDP_PSR_TP1_TP3_SEL			(1 << 11)
@@ -4140,6 +4141,12 @@ enum {
 #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
+#define   EDP_PSR_TP4_TIME_SHIFT		(6)
+#define   EDP_PSR_TP4_TIME_MASK			(0xC0) /* ICL+ */
+#define   EDP_PSR_TP4_TIME_500us		(0 << EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
+#define   EDP_PSR_TP4_TIME_100us		(1 << EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
+#define   EDP_PSR_TP4_TIME_2500us		(2 << EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
+#define   EDP_PSR_TP4_TIME_0us			(3 << EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
 #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
 #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index a9f40985a621..d967d9fb41d3 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -238,7 +238,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
  * or for 1.4 devices that support it, training Pattern 3 for HBR2
  * or 1.2 devices that support it, Training Pattern 2 otherwise.
  */
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
+u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 {
 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bf1c38728a59..76d158024192 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1691,6 +1691,7 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 					    int link_rate, uint8_t lane_count);
 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
+u32 intel_dp_training_pattern(struct intel_dp *intel_dp);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
 			  struct drm_modeset_acquire_ctx *ctx);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6838b525502..b82debd5573b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -385,20 +385,34 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	else
 		val |= EDP_PSR_TP1_TIME_2500us;
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) {
 		val |=  EDP_PSR_TP2_TP3_TIME_0us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+		if (INTEL_GEN(dev_priv) >= 11)
+			val |= EDP_PSR_TP4_TIME_0us;
+	} else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) {
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+		if (INTEL_GEN(dev_priv) >= 11)
+			val |= EDP_PSR_TP4_TIME_100us;
+	} else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) {
 		val |= EDP_PSR_TP2_TP3_TIME_500us;
-	else
+		if (INTEL_GEN(dev_priv) >= 11)
+			val |= EDP_PSR_TP4_TIME_500us;
+	} else {
 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
+		if (INTEL_GEN(dev_priv) >= 11)
+			val |= EDP_PSR_TP4_TIME_2500us;
+	}
 
-	if (intel_dp_source_supports_hbr2(intel_dp) &&
-	    drm_dp_tps3_supported(intel_dp->dpcd))
+	switch (intel_dp_training_pattern(intel_dp)) {
+	case DP_TRAINING_PATTERN_4:
+		val |= EDP_PSR_TP4_SEL;
+		break;
+	case DP_TRAINING_PATTERN_3:
 		val |= EDP_PSR_TP1_TP3_SEL;
-	else
+		break;
+	default:
 		val |= EDP_PSR_TP1_TP2_SEL;
+	}
 
 	if (INTEL_GEN(dev_priv) >= 8)
 		val |= EDP_PSR_CRC_ENABLE;
-- 
2.19.0