[PATCH] clear
Matthew Auld
matthew.auld at intel.com
Tue Apr 2 22:41:01 UTC 2019
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_blt.c | 335 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_blt.h | 17 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/selftests/huge_pages.c | 19 +-
7 files changed, 378 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_blt.c
create mode 100644 drivers/gpu/drm/i915/i915_blt.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30bf3301ea24..ea547bda0215 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -35,7 +35,8 @@ subdir-ccflags-y += \
# Please keep these build lists sorted!
# core driver code
-i915-y := i915_drv.o \
+i915-y := i915_blt.o \
+ i915_drv.o \
i915_irq.o \
i915_memcpy.o \
i915_mm.o \
diff --git a/drivers/gpu/drm/i915/i915_blt.c b/drivers/gpu/drm/i915/i915_blt.c
new file mode 100644
index 000000000000..e3cb25f2edd8
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_blt.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_blt.h"
+
+#include "intel_drv.h"
+
+static struct i915_vma *
+__i915_fill_blt(struct i915_vma *vma, u32 value)
+{
+ struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
+ const int gen = INTEL_GEN(i915);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *batch;
+ u32 *cmd;
+ int err;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ if (gen >= 8) {
+ *cmd++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7-2);
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cmd++ = 0;
+ *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = upper_32_bits(vma->node.start);
+ *cmd++ = value;
+ *cmd++ = MI_NOOP;
+ } else {
+ *cmd++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
+ *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cmd++ = vma->node.start;
+ *cmd++ = value;
+ *cmd++ = MI_NOOP;
+ }
+
+ *cmd = MI_BATCH_BUFFER_END;
+ i915_gem_chipset_flush(i915);
+
+ i915_gem_object_unpin_map(obj);
+
+ batch = i915_vma_instance(obj, vma->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto err;
+
+ return batch;
+
+err:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static int i915_fill_blt(struct i915_gem_context *ctx,
+ struct i915_vma *vma,
+ u32 value)
+{
+ struct drm_i915_private *i915 = to_i915(vma->obj->base.dev);
+ struct intel_engine_cs *engine = i915->engine[BCS0];
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ int flags = 0;
+ int err;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ batch = __i915_fill_blt(vma, value);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_request;
+ }
+
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unpin(batch);
+ i915_vma_close(batch);
+ if (err) {
+ i915_gem_object_put(batch->obj);
+ goto err_request;
+ }
+
+ i915_gem_object_set_active_reference(batch->obj);
+
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ flags);
+ if (err)
+ goto err_request;
+
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ if (err)
+ i915_request_skip(rq, err);
+
+err_request:
+ i915_request_add(rq);
+ return err;
+}
+
+static int i915_gem_object_fill_blt(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *obj,
+ u32 value)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_address_space *vm;
+ struct i915_vma *vma;
+ int err;
+
+ lockdep_assert_held(&i915->drm.struct_mutex);
+
+ vm = ctx->ppgtt ? &ctx->ppgtt->vm : &i915->ggtt.vm;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ return err;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_vma_close(vma);
+ return err;
+ }
+
+ err = i915_fill_blt(ctx, vma, value);
+ i915_vma_unpin(vma);
+ i915_vma_close(vma);
+
+ return err;
+}
+
+static int i915_gem_object_clear_blt(struct i915_gem_context *ctx,
+ struct drm_i915_gem_object *obj)
+{
+ return i915_gem_object_fill_blt(ctx, obj, 0);
+}
+
+static struct drm_i915_gem_object *
+create_sleeve(struct drm_i915_private *i915,
+ struct sg_table *pages,
+ unsigned int page_sizes,
+ u64 size)
+{
+ struct drm_i915_gem_object *sleeve;
+
+ /* XXX: sketchy af */
+ sleeve = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(sleeve))
+ return sleeve;
+
+ mutex_lock(&sleeve->mm.lock);
+
+ atomic_inc(&sleeve->mm.pages_pin_count);
+ __i915_gem_object_set_pages(sleeve, pages, page_sizes);
+
+ mutex_unlock(&sleeve->mm.lock);
+
+ return sleeve;
+}
+
+static void destroy_sleeve(struct drm_i915_gem_object *sleeve)
+{
+ mutex_lock(&sleeve->mm.lock);
+
+ __i915_gem_object_unset_pages(sleeve);
+ atomic_dec(&sleeve->mm.pages_pin_count);
+
+ mutex_unlock(&sleeve->mm.lock);
+
+ i915_gem_object_put(sleeve);
+}
+
+struct clear_pages_work {
+ struct dma_fence dma;
+ struct i915_sw_fence wait;
+ struct work_struct work;
+ struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *sleeve;
+ struct i915_gem_context *ctx;
+};
+
+static const char *clear_pages_work_driver_name(struct dma_fence *fence)
+{
+ return DRIVER_NAME;
+}
+
+static const char *clear_pages_work_timeline_name(struct dma_fence *fence)
+{
+ return "clear";
+}
+
+static void clear_pages_work_release(struct dma_fence *fence)
+{
+ struct clear_pages_work *w = container_of(fence, typeof(*w), dma);
+
+ i915_sw_fence_fini(&w->wait);
+
+ BUILD_BUG_ON(offsetof(typeof(*w), dma));
+ dma_fence_free(&w->dma);
+}
+
+static const struct dma_fence_ops clear_pages_work_ops = {
+ .get_driver_name = clear_pages_work_driver_name,
+ .get_timeline_name = clear_pages_work_timeline_name,
+ .release = clear_pages_work_release,
+};
+
+static void i915_clear_pages_worker(struct work_struct *work)
+{
+ struct clear_pages_work *w = container_of(work, typeof(*w), work);
+ struct drm_i915_private *i915 = to_i915(w->obj->base.dev);
+ intel_wakeref_t wakeref;
+ int err;
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ mutex_lock(&i915->drm.struct_mutex);
+ err = i915_gem_object_clear_blt(w->ctx, w->sleeve);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ intel_runtime_pm_put(i915, wakeref);
+
+ GEM_BUG_ON(err);
+
+ err = i915_gem_object_wait(w->sleeve,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ GEM_BUG_ON(err);
+
+ mutex_lock(&i915->drm.struct_mutex);
+ err = i915_gem_object_unbind(w->sleeve);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ GEM_BUG_ON(err);
+
+ mutex_lock(&w->obj->mm.lock);
+ __i915_gem_object_set_pages(w->obj, w->sleeve->mm.pages,
+ w->sleeve->mm.page_sizes.phys);
+ mutex_unlock(&w->obj->mm.lock);
+
+ i915_gem_object_put(w->obj);
+ i915_gem_context_put(w->ctx);
+
+ destroy_sleeve(w->sleeve);
+
+ dma_fence_signal(&w->dma);
+ dma_fence_put(&w->dma);
+}
+
+static int __i915_sw_fence_call
+clear_pages_work_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct clear_pages_work *w = container_of(fence, typeof(*w), wait);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ schedule_work(&w->work);
+ break;
+
+ case FENCE_FREE:
+ dma_fence_put(&w->dma);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static DEFINE_SPINLOCK(fence_lock);
+
+int i915_schedule_clear_pages_blt(struct drm_i915_gem_object *obj,
+ struct i915_gem_context *ctx,
+ struct sg_table *pages,
+ unsigned int page_sizes,
+ u64 size)
+{
+ struct drm_i915_gem_object *sleeve;
+ struct clear_pages_work *work;
+
+ sleeve = create_sleeve(ctx->i915, pages, page_sizes, size);
+ if (IS_ERR(sleeve))
+ return PTR_ERR(sleeve);
+
+ work = kmalloc(sizeof(*work), GFP_KERNEL);
+ if (work == NULL) {
+ destroy_sleeve(sleeve);
+ return -ENOMEM;
+ }
+
+ work->sleeve = sleeve;
+ work->obj = i915_gem_object_get(obj);
+ work->ctx = i915_gem_context_get(ctx);
+
+ INIT_WORK(&work->work, i915_clear_pages_worker);
+
+ dma_fence_init(&work->dma,
+ &clear_pages_work_ops,
+ &fence_lock,
+ to_i915(obj->base.dev)->mm.unordered_timeline,
+ 0);
+ i915_sw_fence_init(&work->wait, clear_pages_work_notify);
+
+ i915_gem_object_lock(obj);
+ GEM_BUG_ON(!reservation_object_test_signaled_rcu(obj->resv, true));
+
+ i915_sw_fence_await_reservation(&work->wait,
+ obj->resv, NULL,
+ true, I915_FENCE_TIMEOUT,
+ I915_FENCE_GFP);
+ reservation_object_add_excl_fence(obj->resv, &work->dma);
+
+ i915_gem_object_unlock(obj);
+
+ dma_fence_get(&work->dma);
+ i915_sw_fence_commit(&work->wait);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_blt.h b/drivers/gpu/drm/i915/i915_blt.h
new file mode 100644
index 000000000000..cd8eef9c0565
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_blt.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_BLT_H__
+#define __I915_BLT_H__
+
+#include "i915_drv.h"
+
+int i915_schedule_clear_pages_blt(struct drm_i915_gem_object *obj,
+ struct i915_gem_context *ctx,
+ struct sg_table *pages,
+ unsigned int page_sizes,
+ u64 size);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ab4826921f7..6c2a44be27cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3010,6 +3010,9 @@ int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
enum i915_mm_subclass subclass);
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
+struct sg_table *
+__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj);
+
enum i915_map_type {
I915_MAP_WB = 0,
I915_MAP_WC,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bf594a5e88bc..2377b2cc7eda 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -39,6 +39,7 @@
#include <linux/dma-buf.h>
#include <linux/mman.h>
+#include "i915_blt.h"
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gemfs.h"
@@ -2239,7 +2240,7 @@ static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
rcu_read_unlock();
}
-static struct sg_table *
+struct sg_table *
__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
@@ -2588,17 +2589,12 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
- int err;
-
if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
DRM_DEBUG("Attempting to obtain a purgeable object\n");
return -EFAULT;
}
- err = obj->ops->get_pages(obj);
- GEM_BUG_ON(!err && !i915_gem_object_has_pages(obj));
-
- return err;
+ return obj->ops->get_pages(obj);
}
/* Ensure that the associated pages are gathered from the backing storage
diff --git a/drivers/gpu/drm/i915/intel_gpu_commands.h b/drivers/gpu/drm/i915/intel_gpu_commands.h
index a34ece53a771..7e95827b0726 100644
--- a/drivers/gpu/drm/i915/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/intel_gpu_commands.h
@@ -180,6 +180,7 @@
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
+#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22)
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 90721b54e7ae..afd992a5e474 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -66,6 +66,7 @@ static void huge_pages_free_pages(struct sg_table *st)
static int get_huge_pages(struct drm_i915_gem_object *obj)
{
#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
unsigned int page_mask = obj->mm.page_mask;
struct sg_table *st;
struct scatterlist *sg;
@@ -100,7 +101,7 @@ static int get_huge_pages(struct drm_i915_gem_object *obj)
struct page *page;
GEM_BUG_ON(order >= MAX_ORDER);
- page = alloc_pages(GFP | __GFP_ZERO, order);
+ page = alloc_pages(GFP, order);
if (!page)
goto err;
@@ -126,7 +127,10 @@ static int get_huge_pages(struct drm_i915_gem_object *obj)
obj->mm.madv = I915_MADV_DONTNEED;
GEM_BUG_ON(sg_page_sizes != obj->mm.page_mask);
- __i915_gem_object_set_pages(obj, st, sg_page_sizes);
+
+ if (i915_schedule_clear_pages_blt(obj, i915->kernel_context, st,
+ sg_page_sizes, obj->base.size))
+ goto err;
return 0;
@@ -1269,6 +1273,17 @@ static int igt_ppgtt_exhaust_huge(void *arg)
goto out_device;
}
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ /* XXX: sync the object clear without holding the bkl */
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ GEM_BUG_ON(err);
+
+ mutex_lock(&i915->drm.struct_mutex);
+
/* Force the page-size for the gtt insertion */
obj->mm.page_sizes.sg = page_sizes;
--
2.20.1
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