[PATCH 0/3] Fix mipi dsi pipe_config mismatch for icl
Vandita Kulkarni
vandita.kulkarni at intel.com
Mon Apr 8 15:52:11 UTC 2019
This is series fixes the WARN_ON that we see due to
pipe_config mismatch on mipi dsi for icl.
Only DSI0 trancoder regs are read even in case of dual link mode
as the values programmed for DSI0 and DSI1 transcoder registers
Vandita Kulkarni (3):
drm/i915: Fix pipe config timing mismatch warnings
drm/i915: Fix pipe config mismatch for bpp, output format
drm/i915: Fix pixel clock and crtc clock config mismatch
drivers/gpu/drm/i915/icl_dsi.c | 88 +++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 3 +-
2 files changed, 89 insertions(+), 2 deletions(-)
--
2.21.0.5.gaeb582a
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