[PATCH 1/2] drm/i915/icl: Don't try to reset single RPS IIR bit more than once

[Michal Wajdeczko]

We don't expect any new RPS events to arrive while we are servicing
GT INT DW, so single clear of INST IIR should be enough.

Bspec: 21144
References: commit d02b98b8e2 ("drm/i915/icl: Handle RPS interrupts correctly for Gen11")
Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_irq.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d934545445e1..e8eac52acd86 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -487,12 +487,8 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
-
-	while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
-		;
-
+	gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM);
 	dev_priv->gt_pm.rps.pm_iir = 0;
-
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-- 
2.19.2