[PATCH 02/52] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

[Chris Wilson]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.

Whitelist the register to allow media re-configuring it to their liking.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: kevin.ma at intel.com
Cc: xiaogang.li at intel.com
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b3cbed1ee1c9..03824c892d0c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1070,6 +1070,9 @@ static void icl_whitelist_build(struct i915_wa_list *w)
 
 	/* WaAllowUMDToModifySamplerMode:icl */
 	whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+	/* WaEnableStateCacheRedirectToCS:icl */
+	whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
-- 
2.20.1