[PATCH 03/17] drm/i915: Try an alternate means of flushing GGTT indirection

[Chris Wilson]

Replace the mmio readback (that requires spinlock protection against
concurrent cacheline access) with a boring mb().

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d48ec9a76ed1..442595df5a44 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -176,9 +176,6 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 
 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 {
-	struct drm_i915_private *i915 = gt->i915;
-	intel_wakeref_t wakeref;
-
 	/*
 	 * No actual flushing is required for the GTT write domain for reads
 	 * from the GTT domain. Writes to it "immediately" go to main memory
@@ -200,18 +197,21 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 
 	wmb();
 
-	if (INTEL_INFO(i915)->has_coherent_ggtt)
+	if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 		return;
 
-	intel_gt_chipset_flush(gt);
+	if (INTEL_GEN(gt->i915) < 6)
+		intel_gtt_chipset_flush();
 
-	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
-		struct intel_uncore *uncore = gt->uncore;
+	if (intel_gt_pm_get_if_awake(gt)) {
+		unsigned long flags;
 
-		spin_lock_irq(&uncore->lock);
-		intel_uncore_posting_read_fw(uncore,
+		spin_lock_irqsave(&gt->irq_lock, flags);
+		intel_uncore_posting_read_fw(gt->uncore,
 					     RING_HEAD(RENDER_RING_BASE));
-		spin_unlock_irq(&uncore->lock);
+		spin_unlock_irqrestore(&gt->irq_lock, flags);
+
+		intel_gt_pm_put(gt);
 	}
 }
 
-- 
2.23.0.rc1