[PATCH 2/2] drm/i915/gt: Avoid mmio reads when setting up interrupts from idle

[Chris Wilson]

If we know the submission engine is idle, we do not need to post the
write to enable interrupts as they will be enabled prior to submission.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 89ce3653b4cf..2fa295404b8b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3325,14 +3325,15 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 
 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
 {
-	ENGINE_WRITE(engine, RING_IMR,
-		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
-	ENGINE_POSTING_READ(engine, RING_IMR);
+	ENGINE_WRITE_FW(engine, RING_IMR,
+			~(engine->irq_enable_mask | engine->irq_keep_mask));
+	if (execlists_active(&engine->execlists))
+		ENGINE_POSTING_READ(engine, RING_IMR);
 }
 
 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
 {
-	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
+	ENGINE_WRITE_FW(engine, RING_IMR, ~engine->irq_keep_mask);
 }
 
 static int gen8_emit_flush(struct i915_request *request, u32 mode)
-- 
2.24.1