[PATCH 11/11] fbc debug
José Roberto de Souza
jose.souza at intel.com
Mon Feb 4 23:34:19 UTC 2019
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++
drivers/gpu/drm/i915/intel_fbc.c | 46 ++++++++++++++++++----------
3 files changed, 57 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a496ad71d25c..da19007279d4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3566,6 +3566,7 @@ static void intel_ddi_update_pipe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ DRM_DEBUG_KMS("intel_ddi_update_pipe()\n");
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index df7a7a310f2f..57263c2b5472 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2061,6 +2061,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
struct i915_vma *vma;
unsigned int pinctl;
u32 alignment;
+ bool map_and_fenceable;
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -2102,6 +2103,26 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
if (IS_ERR(vma))
goto err;
+ map_and_fenceable = i915_vma_is_map_and_fenceable(vma);
+ if (uses_fence && !map_and_fenceable) {
+ bool fenceable, mappable;
+
+ fenceable = vma->node.size >= vma->fence_size;
+ fenceable = fenceable && IS_ALIGNED(vma->node.start, vma->fence_alignment);
+
+ mappable = (vma->node.start + vma->fence_size) <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+
+ DRM_DEBUG_KMS("uses_fence=true i915_vma_is_map_and_fenceable(vma)=false | fenceable=%d mappable=%d\n", fenceable, mappable);
+ if (!fenceable) {
+ DRM_DEBUG_KMS("\tvma->node.size >= vma->fence_size=%d\n", vma->node.size >= vma->fence_size);
+ DRM_DEBUG_KMS("\tIS_ALIGNED(vma->node.start, vma->fence_alignment)=%d\n", IS_ALIGNED(vma->node.start, vma->fence_alignment));
+ }
+
+ if (!mappable) {
+ DRM_DEBUG_KMS("\tmappable_end=%llu\n", i915_vm_to_ggtt(vma->vm)->mappable_end);
+ }
+ }
+
if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
int ret;
@@ -2122,6 +2143,9 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
* mode that matches the user configuration.
*/
ret = i915_vma_pin_fence(vma);
+ DRM_DEBUG_KMS("i915_vma_pin_fence() ret=%i vma->fence=%p\n", ret, vma->fence);
+ WARN_ON(i915_gem_object_is_tiled(vma->obj) && (ret < 0 || !vma->fence));
+
if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
i915_gem_object_unpin_from_display_plane(vma);
vma = ERR_PTR(ret);
@@ -12857,12 +12881,14 @@ static void intel_update_crtc(struct drm_crtc *crtc,
to_intel_plane(crtc->primary));
if (modeset) {
+ DRM_DEBUG_KMS("modeset\n");
update_scanline_offset(pipe_config);
dev_priv->display.crtc_enable(pipe_config, state);
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(intel_crtc);
} else {
+ DRM_DEBUG_KMS("fastset\n");
intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 656e684e7c9a..8bc3ae6c088b 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -662,6 +662,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->vma = NULL;
cache->flags = 0;
+ DRM_DEBUG_KMS("intel_fbc_update_state_cache()\n");
+
cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
@@ -681,16 +683,21 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
- if (!cache->plane.visible)
+ if (!cache->plane.visible) {
+ DRM_DEBUG_KMS("\t!cache->plane.visible\n");
return;
+ }
cache->fb.format = fb->format;
cache->fb.stride = fb->pitches[0];
cache->vma = plane_state->vma;
cache->flags = plane_state->flags;
- if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
+ if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence)) {
+ DRM_DEBUG_KMS("\t&= ~PLANE_HAS_FENCEu\n");
cache->flags &= ~PLANE_HAS_FENCE;
+ }
+ DRM_DEBUG_KMS("\tcache->flags=%lu\n", cache->flags);
}
static bool intel_fbc_can_activate(struct intel_crtc *crtc)
@@ -699,73 +706,75 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
struct intel_fbc *fbc = &dev_priv->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
+ DRM_DEBUG_KMS("intel_fbc_can_activate()\n");
+
/* We don't need to use a state cache here since this information is
* global for all CRTC.
*/
if (fbc->underrun_detected) {
fbc->no_fbc_reason = "underrun detected";
- return false;
+ goto fail;
}
if (!cache->vma) {
fbc->no_fbc_reason = "primary plane not visible";
- return false;
+ goto fail;
}
if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
fbc->no_fbc_reason = "incompatible mode";
- return false;
+ goto fail;
}
if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
fbc->no_fbc_reason = "mode too large for compression";
- return false;
+ goto fail;
}
/* The use of a CPU fence is mandatory in order to detect writes
* by the CPU to the scanout and trigger updates to the FBC.
*
* Note that is possible for a tiled surface to be unmappable (and
- * so have no fence associated with it) due to aperture constaints
+ * so have no fence associated with it) due to aperture constraints
* at the time of pinning.
*
* FIXME with 90/270 degree rotation we should use the fence on
* the normal GTT view (the rotated view doesn't even have a
* fence). Would need changes to the FBC fence Y offset as well.
- * For now this will effecively disable FBC with 90/270 degree
+ * For now this will effectively disable FBC with 90/270 degree
* rotation.
*/
if (!(cache->flags & PLANE_HAS_FENCE)) {
fbc->no_fbc_reason = "framebuffer not tiled or fenced";
- return false;
+ goto fail;
}
if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
cache->plane.rotation != DRM_MODE_ROTATE_0) {
fbc->no_fbc_reason = "rotation unsupported";
- return false;
+ goto fail;
}
if (!stride_is_valid(dev_priv, cache->fb.stride)) {
fbc->no_fbc_reason = "framebuffer stride not supported";
- return false;
+ goto fail;
}
if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
fbc->no_fbc_reason = "pixel format is invalid";
- return false;
+ goto fail;
}
if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
cache->fb.format->has_alpha) {
fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
- return false;
+ goto fail;
}
/* WaFbcExceedCdClockThreshold:hsw,bdw */
if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
fbc->no_fbc_reason = "pixel rate is too big";
- return false;
+ goto fail;
}
/* It is possible for the required CFB size change without a
@@ -781,7 +790,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
fbc->compressed_fb.size * fbc->threshold) {
fbc->no_fbc_reason = "CFB requirements changed";
- return false;
+ goto fail;
}
/*
@@ -792,10 +801,15 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
if (IS_GEN_RANGE(dev_priv, 9, 10) &&
(fbc->state_cache.plane.adjusted_y & 3)) {
fbc->no_fbc_reason = "plane Y offset is misaligned";
- return false;
+ goto fail;
}
+ DRM_DEBUG_KMS("\tret=true\n");
return true;
+
+fail:
+ DRM_DEBUG_KMS("\tret=false no_fbc_reason=%s\n", fbc->no_fbc_reason);
+ return false;
}
static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
--
2.20.1
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