[PATCH 24/46] sem

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_pmu.c | 31 +++++++++++--------------------
 1 file changed, 11 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e22e1d2025ff..24bae1d45c63 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -101,7 +101,7 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
 	 *
 	 * Use RCS as proxy for all engines.
 	 */
-	else if (intel_engine_supports_stats(i915->engine[RCS]))
+	else if (i915->caps.scheduler & I915_SCHEDULER_CAP_PMU)
 		enable &= ~BIT(I915_SAMPLE_BUSY);
 
 	/*
@@ -171,32 +171,23 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
 	if (!wakeref)
 		return;
 
-	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 	for_each_engine(engine, dev_priv, id) {
 		typeof(engine->pmu) *pmu = &engine->pmu;
 		u32 val;
 
-		if (pmu->enable & BIT(I915_SAMPLE_BUSY)) {
-			val = I915_READ_FW(RING_MI_MODE(engine->mmio_base));
-			if (!(val & MODE_IDLE))
-				add_sample(&pmu->sample[I915_SAMPLE_BUSY],
-					   period_ns);
-		}
-
-		if (pmu->enable &
-		    (BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA))) {
-			val = I915_READ_FW(RING_CTL(engine->mmio_base));
+		val = I915_READ_FW(RING_CTL(engine->mmio_base));
+		if (val == 0 || val == ~0u)
+			continue;
 
-			if (val & RING_WAIT)
-				add_sample(&pmu->sample[I915_SAMPLE_WAIT],
-					   period_ns);
+		if (val & RING_WAIT)
+			add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
+		if (val & RING_WAIT_SEMAPHORE)
+			add_sample(&pmu->sample[I915_SAMPLE_SEMA], period_ns);
 
-			if (val & RING_WAIT_SEMAPHORE)
-				add_sample(&pmu->sample[I915_SAMPLE_SEMA],
-					   period_ns);
-		}
+		val = I915_READ_FW(RING_MI_MODE(engine->mmio_base));
+		if (!(val & MODE_IDLE))
+			add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
 	}
-	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
 	intel_runtime_pm_put(dev_priv, wakeref);
 }
-- 
2.20.1