[PATCH 40/40] drm/i915: Eliminate posting reads after enabling breadcrumbs irq

[Chris Wilson]

We kept the posting read after enabling the RING_IMR for the breadcrumbs
irq in order to be sure the HW had completed its switch before sleeping
for the interrupt. The posting read has survived several years beyond
its merit due to the persistent trouble we had with breadcrumb/interrupt
serialisation, but now we^WI believe that we have those resolved and so
can remove the redundant mmio flush.

Testcase: igt/gem_sync
References: 0f46832fab77 ("drm/i915: Mask USER interrupts on gen6 (until required)")
References: 31bb59cc01fd ("drm/i915: Move the get/put irq locking into the caller")
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_irq.c         | 1 -
 drivers/gpu/drm/i915/intel_lrc.c        | 3 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 --
 3 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9e7bb5977829..ef6912bdb8ce 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -350,7 +350,6 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 {
 	ilk_update_gt_irq(dev_priv, mask, mask);
-	POSTING_READ_FW(GTIMR);
 }
 
 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9a9768258efb..2636358169b0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1909,14 +1909,15 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
+
 	I915_WRITE_IMR(engine,
 		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
-	POSTING_READ_FW(RING_IMR(engine->mmio_base));
 }
 
 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
+
 	I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a3d4b013e099..e9b43e332abe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -978,7 +978,6 @@ i9xx_irq_enable(struct intel_engine_cs *engine)
 
 	dev_priv->irq_mask &= ~engine->irq_enable_mask;
 	I915_WRITE(IMR, dev_priv->irq_mask);
-	POSTING_READ_FW(RING_IMR(engine->mmio_base));
 }
 
 static void
@@ -997,7 +996,6 @@ i8xx_irq_enable(struct intel_engine_cs *engine)
 
 	dev_priv->irq_mask &= ~engine->irq_enable_mask;
 	I915_WRITE16(IMR, dev_priv->irq_mask);
-	POSTING_READ16(RING_IMR(engine->mmio_base));
 }
 
 static void
-- 
2.20.1