[PATCH 38/40] drm/i915: Identify active requests

Chris Wilson chris at chris-wilson.co.uk
Tue Jan 1 17:16:40 UTC 2019


To allow requests to forgo a common execution timeline, one question we
need to be able to answer is "is this request running?". To track
whether a request has started on HW, we can emit a breadcrumb at the
beginning of the request and check its timeline's HWSP to see if the
breadcrumb has advanced past the start of this request. (This is in
contrast to the global timeline where we need only ask if we are on the
global timeline and if the timeline has advanced past the end of the
previous request.)

There is still confusion from a preempted request, which has already
started but relinquished the HW to a high priority request. For the
common case, this discrepancy should be negligible. However, for
identification of hung requests, knowing which one was running at the
time of the hang will be much more important.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_request.c     |  8 +++----
 drivers/gpu/drm/i915/i915_request.h     |  1 +
 drivers/gpu/drm/i915/intel_engine_cs.c  |  4 +++-
 drivers/gpu/drm/i915/intel_lrc.c        | 21 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index ec4dbc67ef9e..6ab72679c44c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -597,7 +597,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
 		       &i915_fence_ops,
 		       &rq->lock,
 		       rq->timeline->fence_context,
-		       timeline_get_seqno(rq->timeline));
+		       2 * timeline_get_seqno(rq->timeline));
 
 	/* We bump the ref for the fence chain */
 	i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
@@ -645,7 +645,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
 	rq->infix = rq->ring->emit; /* end of header; start of user payload */
 
 	/* Check that we didn't interrupt ourselves with a new request */
-	GEM_BUG_ON(rq->timeline->seqno != rq->fence.seqno);
+	GEM_BUG_ON(2 * rq->timeline->seqno != rq->fence.seqno);
 	return rq;
 
 err_unwind:
@@ -860,7 +860,7 @@ void i915_request_add(struct i915_request *request)
 	 * our i915_request_alloc() and called __i915_request_add() before
 	 * us, the timeline will hold its seqno which is later than ours.
 	 */
-	GEM_BUG_ON(timeline->seqno != request->fence.seqno);
+	GEM_BUG_ON(2 * timeline->seqno != request->fence.seqno);
 
 	/*
 	 * To ensure that this call will not fail, space for its emissions
@@ -903,7 +903,7 @@ void i915_request_add(struct i915_request *request)
 	list_add_tail(&request->link, &timeline->requests);
 	spin_unlock_irq(&timeline->lock);
 
-	GEM_BUG_ON(timeline->seqno != request->fence.seqno);
+	GEM_BUG_ON(2 * timeline->seqno != request->fence.seqno);
 	i915_gem_active_set(&timeline->last_request, request);
 
 	list_add_tail(&request->ring_link, &ring->request_list);
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 344e52b53ccd..084d174ba83b 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -311,6 +311,7 @@ static inline void i915_request_fake_complete(const struct i915_request *rq)
  */
 static inline bool i915_request_started(const struct i915_request *rq)
 {
+	/* Remember: started but may have since been preempted! */
 	return i915_seqno_passed(i915_request_hwsp(rq), rq->fence.seqno - 1);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8c30fc91a92e..f894da66aba8 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1234,7 +1234,9 @@ static void print_request(struct drm_printer *m,
 	drm_printf(m, "%s%x%s [%llx:%llx]%s @ %dms: %s\n",
 		   prefix,
 		   rq->global_seqno,
-		   i915_request_completed(rq) ? "!" : "",
+		   i915_request_completed(rq) ? "!" :
+		   i915_request_started(rq) ? "*" :
+		   "",
 		   rq->fence.context, rq->fence.seqno,
 		   buf,
 		   jiffies_to_msecs(jiffies - rq->emitted_jiffies),
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c1dfc87ff81..9a9768258efb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1259,6 +1259,23 @@ execlists_context_pin(struct intel_engine_cs *engine,
 	return __execlists_context_pin(engine, ctx, ce);
 }
 
+static int emit_initial_breadcrumb(struct i915_request *rq)
+{
+	u32 *cs;
+
+	cs = intel_ring_begin(rq, 4);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+	*cs++ = i915_timeline_seqno_address(rq->timeline);
+	*cs++ = 0;
+	*cs++ = rq->fence.seqno - 1;
+
+	intel_ring_advance(rq, cs);
+	return 0;
+}
+
 static int emit_pdps(struct i915_request *rq)
 {
 	const struct intel_engine_cs * const engine = rq->engine;
@@ -1333,6 +1350,10 @@ static int execlists_request_alloc(struct i915_request *request)
 	 * to cancel/unwind this request now.
 	 */
 
+	ret = emit_initial_breadcrumb(request);
+	if (ret)
+		return ret;
+
 	/* Unconditionally invalidate GPU caches and TLBs. */
 	if (i915_vm_is_48bit(&request->gem_context->ppgtt->vm))
 		ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1b02433c38a9..0831c9dba80a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1916,6 +1916,30 @@ static int switch_context(struct i915_request *rq)
 	return ret;
 }
 
+static int emit_initial_breadcrumb(struct i915_request *rq)
+{
+	u32 *cs;
+
+	cs = intel_ring_begin(rq, 4);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	if (INTEL_GEN(rq->i915) >= 4) {
+		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+		*cs++ = 0;
+		*cs++ = i915_timeline_seqno_address(rq->timeline);
+		*cs++ = rq->fence.seqno - 1;
+	} else {
+		*cs++ = MI_STORE_DWORD_IMM | MI_USE_GGTT;
+		*cs++ = i915_timeline_seqno_address(rq->timeline);
+		*cs++ = rq->fence.seqno - 1;
+		*cs++ = MI_NOOP;
+	}
+
+	intel_ring_advance(rq, cs);
+	return 0;
+}
+
 static int ring_request_alloc(struct i915_request *request)
 {
 	int ret;
@@ -1929,6 +1953,10 @@ static int ring_request_alloc(struct i915_request *request)
 	 */
 	request->reserved_space += LEGACY_REQUEST_SIZE;
 
+	ret = emit_initial_breadcrumb(request);
+	if (ret)
+		return ret;
+
 	ret = switch_context(request);
 	if (ret)
 		return ret;
-- 
2.20.1



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