[PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v11)
Bob Paauwe
bob.j.paauwe at intel.com
Thu Jan 17 18:43:15 UTC 2019
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.
Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.
v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
Remove unnecessary line coninuations (Bob)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
v8: gvt is actually full ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
v11: rebase on current drm-tip
Signed-off-by: Bob Paauwe <bob.j.paauwe at intel.com>
CC: Rodrigo Vivi <rodrigo.vivi at intel.com>
CC: Michel Thierry <michel.thierry at intel.com>
CC: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 130 ++++++++----------
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +
drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 8 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +
15 files changed, 85 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index d94e9989af82..b097b380af57 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1105,7 +1105,7 @@ i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
int i;
- if (i915_vm_is_48bit(&i915_ppgtt->vm))
+ if (i915_vm_is_4lvl(&i915_ppgtt->vm))
px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
else {
for (i = 0; i < GEN8_3LVL_PDPES; i++)
@@ -1158,7 +1158,7 @@ i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
int i;
- if (i915_vm_is_48bit(&i915_ppgtt->vm))
+ if (i915_vm_is_4lvl(&i915_ppgtt->vm))
s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
else {
for (i = 0; i < GEN8_3LVL_PDPES; i++)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index e1c860f80eb0..8a224226396e 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
- vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dafbbfadd1ad..bccea37eba76 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1378,7 +1378,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
if (HAS_PPGTT(dev_priv)) {
if (intel_vgpu_active(dev_priv) &&
- !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+ !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
i915_report_error(dev_priv,
"incompatible vGPU found, support for isolated ppGTT required\n");
return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index da055a86db4d..6d7c4bc4fb1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2444,7 +2444,7 @@ static inline unsigned int i915_sg_segment_size(void)
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv) \
+#define HAS_4LVL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 5933adbe3d99..5299fad9b7c2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -306,7 +306,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
address_mode = INTEL_LEGACY_32B_CONTEXT;
- if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+ if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
address_mode = INTEL_LEGACY_64B_CONTEXT;
desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d24628f184e4..1e5a03567633 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -578,13 +578,13 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
* page-table operating in 64K mode must point to a properly aligned 64K
* region, including any PTEs which happen to point to scratch.
*
- * This is only relevant for the 48b PPGTT where we support
+ * This is only relevant for the 4-level PPGTT where we support
* huge-gtt-pages, see also i915_vma_insert(). However, as we share the
* scratch (read-only) between all vm, we create one 64k scratch page
* for all.
*/
size = I915_GTT_PAGE_SIZE_4K;
- if (i915_vm_is_48bit(vm) &&
+ if (i915_vm_is_4lvl(vm) &&
HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
size = I915_GTT_PAGE_SIZE_64K;
gfp |= __GFP_NOWARN;
@@ -728,7 +728,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
static inline bool use_4lvl(const struct i915_address_space *vm)
{
- return i915_vm_is_48bit(vm);
+ return i915_vm_is_4lvl(vm);
}
static struct i915_page_directory_pointer *
@@ -1526,38 +1526,14 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
* space.
*
*/
-static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
+static int gen8_ppgtt_create(struct i915_hw_ppgtt *ppgtt)
{
- struct i915_hw_ppgtt *ppgtt;
+ struct drm_i915_private *i915 = ppgtt->vm.i915;
int err;
- ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
- if (!ppgtt)
- return ERR_PTR(-ENOMEM);
-
- kref_init(&ppgtt->ref);
-
- ppgtt->vm.i915 = i915;
- ppgtt->vm.dma = &i915->drm.pdev->dev;
-
- ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
- 1ULL << 48 :
- 1ULL << 32;
-
- /* From bdw, there is support for read-only pages in the PPGTT. */
- ppgtt->vm.has_read_only = true;
-
- i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
-
- /* There are only few exceptions for gen >=6. chv and bxt.
- * And we are not sure about the latter so play safe for now.
- */
- if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
- ppgtt->vm.pt_kmap_wc = true;
-
err = gen8_init_scratch(&ppgtt->vm);
if (err)
- goto err_free;
+ return err;
if (use_4lvl(&ppgtt->vm)) {
err = setup_px(&ppgtt->vm, &ppgtt->pml4);
@@ -1581,7 +1557,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
goto err_scratch;
}
}
-
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
@@ -1592,18 +1567,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
- ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
- ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
- ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
- ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
- return ppgtt;
+ return 0;
err_scratch:
gen8_free_scratch(&ppgtt->vm);
-err_free:
- kfree(ppgtt);
- return ERR_PTR(err);
+ return err;
}
/* Write pde (index) from the page directory @pd to the page table @pt */
@@ -1979,54 +1947,30 @@ void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
i915_vma_unpin(ppgtt->vma);
}
-static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
+static int gen6_ppgtt_create(struct gen6_hw_ppgtt *ppgtt,
+ struct i915_ggtt * const ggtt)
{
- struct i915_ggtt * const ggtt = &i915->ggtt;
- struct gen6_hw_ppgtt *ppgtt;
int err;
- ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
- if (!ppgtt)
- return ERR_PTR(-ENOMEM);
-
- kref_init(&ppgtt->base.ref);
-
- ppgtt->base.vm.i915 = i915;
- ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
- ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
-
- i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
-
ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
- ppgtt->base.vm.vma_ops.bind_vma = ppgtt_bind_vma;
- ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
- ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
- ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
err = gen6_ppgtt_init_scratch(ppgtt);
if (err)
- goto err_free;
+ return err;
ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
if (IS_ERR(ppgtt->vma)) {
err = PTR_ERR(ppgtt->vma);
- goto err_scratch;
+ gen6_ppgtt_free_scratch(&ppgtt->base.vm);
+ return err;
}
- return &ppgtt->base;
-
-err_scratch:
- gen6_ppgtt_free_scratch(&ppgtt->base.vm);
-err_free:
- kfree(ppgtt);
- return ERR_PTR(err);
+ return 0;
}
static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
@@ -2078,10 +2022,48 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
static struct i915_hw_ppgtt *
__hw_ppgtt_create(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) < 8)
- return gen6_ppgtt_create(i915);
- else
- return gen8_ppgtt_create(i915);
+ struct gen6_hw_ppgtt *ppgtt;
+ struct i915_address_space *vm;
+ int err;
+
+ ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+ if (!ppgtt)
+ return ERR_PTR(-ENOMEM);
+
+ vm = &ppgtt->base.vm;
+
+ kref_init(&ppgtt->base.ref);
+
+ vm->i915 = i915;
+ vm->dma = &i915->drm.pdev->dev;
+
+ vm->total = BIT_ULL(INTEL_INFO(i915)->ppgtt_bits);
+
+ /* From bdw, there is support for read-only pages in the PPGTT. */
+ vm->has_read_only = (INTEL_GEN(i915) < 8) ? false : true;
+
+ i915_address_space_init(vm, VM_CLASS_PPGTT);
+
+ /* There are only few exceptions for gen >= 6. chv and bxt.
+ * And we are not sure abou the latter so play safe for now.
+ */
+ if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
+ vm->pt_kmap_wc = true;
+
+ err = (INTEL_GEN(i915) < 8) ? gen6_ppgtt_create(ppgtt, &i915->ggtt) :
+ gen8_ppgtt_create(&ppgtt->base);
+
+ if (err) {
+ kfree(ppgtt);
+ return ERR_PTR(err);
+ }
+
+ vm->vma_ops.bind_vma = ppgtt_bind_vma;
+ vm->vma_ops.unbind_vma = ppgtt_unbind_vma;
+ vm->vma_ops.set_pages = ppgtt_set_pages;
+ vm->vma_ops.clear_pages = clear_pages;
+
+ return &ppgtt->base;
}
struct i915_hw_ppgtt *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9229b03d629b..53a66c0c9735 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -367,7 +367,7 @@ struct i915_address_space {
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
{
return (vm->total - 1) >> 32;
}
@@ -507,7 +507,7 @@ static inline u32 gen6_pde_index(u32 addr)
static inline unsigned int
i915_pdpes_per_pdp(const struct i915_address_space *vm)
{
- if (i915_vm_is_48bit(vm))
+ if (i915_vm_is_4lvl(vm))
return GEN8_PML4ES_PER_PML4;
return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dd4aff2b256e..7b4a36e7da72 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -280,6 +280,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.ppgtt = INTEL_PPGTT_ALIASING, \
+ .ppgtt_bits = 31, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
@@ -325,6 +326,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.ppgtt = INTEL_PPGTT_FULL, \
+ .ppgtt_bits = 31, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
@@ -378,6 +380,7 @@ static const struct intel_device_info intel_valleyview_info = {
.display.has_gmch_display = 1,
.display.has_hotplug = 1,
.ppgtt = INTEL_PPGTT_FULL,
+ .ppgtt_bits = 31,
.has_snoop = true,
.has_coherent_ggtt = false,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -425,6 +428,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_bits = 48, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -469,6 +473,7 @@ static const struct intel_device_info intel_cherryview_info = {
.has_logical_ring_contexts = 1,
.display.has_gmch_display = 1,
.ppgtt = INTEL_PPGTT_FULL,
+ .ppgtt_bits = 32,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
@@ -544,6 +549,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_bits = 48, \
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..969e514916ab 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
/*
* VGT capabilities type
*/
-#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
+#define VGT_CAPS_FULL_PPGTT BIT(2)
#define VGT_CAPS_HWSP_EMULATION BIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..0ef78fef5422 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
}
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
{
- return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+ return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
}
struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
void i915_check_vgpu(struct drm_i915_private *dev_priv);
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
static inline bool
intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 957c6527f76b..83e7b9891696 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -190,6 +190,9 @@ struct intel_device_info {
u16 degamma_lut_size;
u16 gamma_lut_size;
} color;
+
+ /* Full PPGTT address range size */
+ int ppgtt_bits;
};
struct intel_runtime_info {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cdc4d84900ff..c56422395187 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1325,7 +1325,7 @@ static int execlists_request_alloc(struct i915_request *request)
*/
/* Unconditionally invalidate GPU caches and TLBs. */
- if (i915_vm_is_48bit(&request->gem_context->ppgtt->vm))
+ if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm))
ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
else
ret = emit_pdps(request);
@@ -2515,7 +2515,7 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
- if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+ if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
/* 64b PPGTT (48bit canonical)
* PDP0_DESCRIPTOR contains the base address to PML4 and
* other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index a52450111802..14a676b1c5a6 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1449,8 +1449,8 @@ static int igt_ppgtt_pin_update(void *arg)
* huge-gtt-pages.
*/
- if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
- pr_info("48b PPGTT not supported, skipping\n");
+ if (!HAS_4LVL_PPGTT(dev_priv)) {
+ pr_info("Extended range PPGTT not supported, skipping\n");
return 0;
}
@@ -1718,8 +1718,8 @@ int i915_gem_huge_page_mock_selftests(void)
goto out_unlock;
}
- if (!i915_vm_is_48bit(&ppgtt->vm)) {
- pr_err("failed to create 48b PPGTT\n");
+ if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+ pr_err("failed to create extended PPGTT\n");
err = -EINVAL;
goto out_close;
}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 3cda66292e76..882f61bb0585 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -183,6 +183,8 @@ struct drm_i915_private *mock_gem_device(void)
I915_GTT_PAGE_SIZE_64K |
I915_GTT_PAGE_SIZE_2M;
+ mkwrite_device_info(i915)->ppgtt_bits = 63;
+
mock_uncore_init(i915);
i915_gem_init__mm(i915);
--
2.19.2
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