[PATCH 7/7] debug

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  3 ++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++++++++++++++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index a4f345ae9244..cd4f49b2f7de 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -986,7 +986,7 @@ read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
 	intel_uncore_forcewake_get__locked(uncore, fw_domains);
 
 	old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-
+printk("old_mcr=%x\n", old_mcr);
 	mcr &= ~mcr_mask;
 	mcr |= mcr_ss;
 	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
@@ -996,6 +996,7 @@ read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
 	mcr &= ~mcr_mask;
 	mcr |= old_mcr & mcr_mask;
 
+printk("restore_mcr=%x\n", mcr);
 	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(uncore, fw_domains);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 94793ebc3e17..2260864b7449 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,6 +948,11 @@ wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
 			  wa->val, wa->mask);
 
 		return false;
+	} else {
+		DRM_DEBUG_DRIVER("%s workaround OK on %s! (%x=%x/%x, expected %x, mask=%x)\n",
+				 name, from, i915_mmio_reg_offset(wa->reg),
+				 cur, cur & wa->read,
+				 wa->val, wa->mask);
 	}
 
 	return true;
@@ -970,7 +975,26 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 	intel_uncore_forcewake_get__locked(uncore, fw);
 
 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
+if (i915_mmio_reg_offset(wa->reg) == i915_mmio_reg_offset(GEN8_MCR_SELECTOR)) {
+printk("GEN8_MCR_SELECTOR before\nmcr=%x\n",
+       intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR));
+}
+if (i915_mmio_reg_offset(wa->reg) == i915_mmio_reg_offset(GEN8_L3SQCREG4)) {
+printk("GEN8_L3SQCREG4 before\nmcr=%x reg=%x\n",
+       intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR),
+       intel_uncore_read_fw(uncore, GEN8_L3SQCREG4));
+}
 		intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
+if (i915_mmio_reg_offset(wa->reg) == i915_mmio_reg_offset(GEN8_MCR_SELECTOR)) {
+printk("GEN8_MCR_SELECTOR after\nmcr=%x\n",
+       intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR));
+}
+if (i915_mmio_reg_offset(wa->reg) == i915_mmio_reg_offset(GEN8_L3SQCREG4)) {
+printk("GEN8_L3SQCREG4 after\nmcr=%x reg=%x mask=%x val=%x\n",
+       intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR),
+       intel_uncore_read_fw(uncore, GEN8_L3SQCREG4),
+       wa->mask, wa->val);
+}
 		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 			wa_verify(wa,
 				  intel_uncore_read_fw(uncore, wa->reg),
-- 
2.20.1