[PATCH 8/8] fix Wa_1604223664

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index dd5117ddb0f1..8b0651aa4921 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1294,7 +1294,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_masked_or(wal,
 				   GEN11_GLBLINVL,
 				   GEN11_BANK_HASH_ADDR_EXCL_MASK,
-				   GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+				   GEN11_BANK_HASH_ADDR_EXCL_BIT7);
 
 		/*
 		 * Wa_1405733216:icl
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..6ad580386535 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8912,7 +8912,7 @@ enum {
 
 #define GEN11_GLBLINVL				_MMIO(0xB404)
 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
-#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT7	(2 << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
-- 
2.20.1