[PATCH 2/2] unicast read all

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 65 +++++++++++++++++++--
 1 file changed, 60 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3493fffc3b97..8fe655911e67 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -938,15 +938,70 @@ wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 	return fw;
 }
 
+static void read_all(struct intel_uncore *uncore, i915_reg_t reg)
+{
+	struct drm_i915_private *i915 = uncore->i915;
+	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+	unsigned int slice, subslice;
+	u32 l3_en, mcr, mcr_mask, common, old_mcr;
+
+	if (!uncore)
+		return;
+
+	if (INTEL_GEN(i915) < 10)
+		return;
+
+	if (is_power_of_2(sseu->slice_mask)) {
+		u32 l3_fuse =
+			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
+			GEN10_L3BANK_MASK;
+
+		l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
+	} else {
+		l3_en = ~0;
+	}
+
+	slice = ffs(sseu->slice_mask) - 1;
+	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+	common = l3_en & sseu->subslice_mask[slice];
+	DRM_DEBUG_DRIVER("l3_en=%x ss_en=%x common=%x\n",
+			 l3_en, sseu->subslice_mask[slice], common);
+
+	old_mcr = intel_uncore_read(uncore, GEN8_MCR_SELECTOR);
+
+	for (subslice = 0; subslice < 8; subslice++) {
+		u32 val;
+
+		if (!(common & BIT(subslice)))
+			continue;
+
+		if (INTEL_GEN(i915) >= 11) {
+			mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+			mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+		} else {
+			mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+			mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+		}
+
+		mcr |= old_mcr & ~(BIT(31) & mcr_mask);
+		intel_uncore_write(uncore, GEN8_MCR_SELECTOR, mcr);
+		val = intel_uncore_read(uncore, reg);
+		DRM_DEBUG_DRIVER("subslice=%u reg=%x val=%u old_mcr=%x mcr=%x\n",
+				 subslice, i915_mmio_reg_offset(reg), val, old_mcr, mcr);
+	}
+
+	intel_uncore_write(uncore, GEN8_MCR_SELECTOR, old_mcr);
+}
+
 static bool
-wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
+wa_verify(struct intel_uncore *uncore, const struct i915_wa *wa, u32 cur, const char *name, const char *from)
 {
 	if ((cur ^ wa->val) & wa->read) {
 		DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
 			  name, from, i915_mmio_reg_offset(wa->reg),
 			  cur, cur & wa->read,
 			  wa->val, wa->mask);
-
+		read_all(uncore, wa->reg);
 		return false;
 	}
 
@@ -972,7 +1027,7 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 		intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
 		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
-			wa_verify(wa,
+			wa_verify(uncore, wa,
 				  intel_uncore_read_fw(uncore, wa->reg),
 				  wal->name, "application");
 	}
@@ -995,7 +1050,7 @@ static bool wa_list_verify(struct intel_uncore *uncore,
 	bool ok = true;
 
 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
-		ok &= wa_verify(wa,
+		ok &= wa_verify(uncore, wa,
 				intel_uncore_read(uncore, wa->reg),
 				wal->name, from);
 
@@ -1524,7 +1579,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
 		if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
 			continue;
 
-		if (!wa_verify(wa, results[i], wal->name, from))
+		if (!wa_verify(NULL, wa, results[i], wal->name, from))
 			err = -ENXIO;
 	}
 
-- 
2.20.1