[PATCH 16/23] drm/i915: Sanitize the shared DPLL find/reference interface
Imre Deak
imre.deak at intel.com
Mon Jun 3 03:25:31 UTC 2019
Pass the PLL HW state to functions where it should be clearer what is
their input.
Move setting the PLL in the crtc_state to the get_dpll() hook, which is
the more logical place for this, where the related PLL HW state was also
set. Clearing the PLL should also happen in a more onion-like way, from
a matched put_dpll() hook, the next patch will do that.
This refactoring is also a preparation for a follow-up patch that will
have to find/reference multiple PLLs.
No functional changes.
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 72 +++++++++++++++++++--------
1 file changed, 50 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index bf4bf64c99dd..487fe92b7f10 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -244,6 +244,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_crtc_state *crtc_state,
+ const struct intel_dpll_hw_state *pll_state,
enum intel_dpll_id range_min,
enum intel_dpll_id range_max)
{
@@ -265,9 +266,9 @@ intel_find_shared_dpll(struct intel_crtc_state *crtc_state,
continue;
}
- if (memcmp(&crtc_state->dpll_hw_state,
+ if (memcmp(pll_state,
&shared_dpll[i].hw_state,
- sizeof(crtc_state->dpll_hw_state)) == 0) {
+ sizeof(*pll_state)) == 0) {
DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
@@ -290,6 +291,7 @@ intel_find_shared_dpll(struct intel_crtc_state *crtc_state,
static void
intel_reference_shared_dpll(struct intel_shared_dpll *pll,
+ const struct intel_dpll_hw_state *pll_state,
struct intel_crtc_state *crtc_state)
{
struct intel_shared_dpll_state *shared_dpll;
@@ -299,10 +301,8 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
if (shared_dpll[id].crtc_mask == 0)
- shared_dpll[id].hw_state =
- crtc_state->dpll_hw_state;
+ shared_dpll[id].hw_state = *pll_state;
- crtc_state->shared_dpll = pll;
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
pipe_name(crtc->pipe));
@@ -440,6 +440,7 @@ ibx_get_dpll(struct intel_crtc_state *crtc_state,
pll->info->name);
} else {
pll = intel_find_shared_dpll(crtc_state,
+ &crtc_state->dpll_hw_state,
DPLL_ID_PCH_PLL_A,
DPLL_ID_PCH_PLL_B);
}
@@ -448,7 +449,10 @@ ibx_get_dpll(struct intel_crtc_state *crtc_state,
return NULL;
/* reference the pll */
- intel_reference_shared_dpll(pll, crtc_state);
+ intel_reference_shared_dpll(pll, &crtc_state->dpll_hw_state,
+ crtc_state);
+
+ crtc_state->shared_dpll = pll;
return pll;
}
@@ -782,6 +786,7 @@ static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(struct intel_crtc_state *
crtc_state->dpll_hw_state.wrpll = val;
pll = intel_find_shared_dpll(crtc_state,
+ &crtc_state->dpll_hw_state,
DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
if (!pll)
@@ -842,6 +847,7 @@ hsw_get_dpll(struct intel_crtc_state *crtc_state,
SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
pll = intel_find_shared_dpll(crtc_state,
+ &crtc_state->dpll_hw_state,
DPLL_ID_SPLL, DPLL_ID_SPLL);
} else {
return NULL;
@@ -850,7 +856,10 @@ hsw_get_dpll(struct intel_crtc_state *crtc_state,
if (!pll)
return NULL;
- intel_reference_shared_dpll(pll, crtc_state);
+ intel_reference_shared_dpll(pll, &crtc_state->dpll_hw_state,
+ crtc_state);
+
+ crtc_state->shared_dpll = pll;
return pll;
}
@@ -1410,16 +1419,21 @@ skl_get_dpll(struct intel_crtc_state *crtc_state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(crtc_state,
+ &crtc_state->dpll_hw_state,
DPLL_ID_SKL_DPLL0,
DPLL_ID_SKL_DPLL0);
else
pll = intel_find_shared_dpll(crtc_state,
+ &crtc_state->dpll_hw_state,
DPLL_ID_SKL_DPLL1,
DPLL_ID_SKL_DPLL3);
if (!pll)
return NULL;
- intel_reference_shared_dpll(pll, crtc_state);
+ intel_reference_shared_dpll(pll, &crtc_state->dpll_hw_state,
+ crtc_state);
+
+ crtc_state->shared_dpll = pll;
return pll;
}
@@ -1851,7 +1865,10 @@ bxt_get_dpll(struct intel_crtc_state *crtc_state,
DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
- intel_reference_shared_dpll(pll, crtc_state);
+ intel_reference_shared_dpll(pll, &crtc_state->dpll_hw_state,
+ crtc_state);
+
+ crtc_state->shared_dpll = pll;
return pll;
}
@@ -2358,6 +2375,7 @@ cnl_get_dpll(struct intel_crtc_state *crtc_state,
}
pll = intel_find_shared_dpll(crtc_state,
+ &crtc_state->dpll_hw_state,
DPLL_ID_SKL_DPLL0,
DPLL_ID_SKL_DPLL2);
if (!pll) {
@@ -2365,7 +2383,10 @@ cnl_get_dpll(struct intel_crtc_state *crtc_state,
return NULL;
}
- intel_reference_shared_dpll(pll, crtc_state);
+ intel_reference_shared_dpll(pll, &crtc_state->dpll_hw_state,
+ crtc_state);
+
+ crtc_state->shared_dpll = pll;
return pll;
}
@@ -2506,7 +2527,8 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
}
static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
- struct intel_encoder *encoder)
+ struct intel_encoder *encoder,
+ struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
u32 cfgcr0, cfgcr1;
@@ -2533,11 +2555,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
DPLL_CFGCR1_PDIV(pll_params.pdiv) |
DPLL_CFGCR1_CENTRAL_FREQ_8400;
- memset(&crtc_state->dpll_hw_state, 0,
- sizeof(crtc_state->dpll_hw_state));
+ memset(pll_state, 0, sizeof(*pll_state));
- crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
- crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
+ pll_state->cfgcr0 = cfgcr0;
+ pll_state->cfgcr1 = cfgcr1;
return true;
}
@@ -2627,10 +2648,10 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
* The specification for this function uses real numbers, so the math had to be
* adapted to integer-only calculation, that's why it looks so different.
*/
-static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state)
+static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
+ struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
int refclk_khz = dev_priv->cdclk.hw.ref;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
@@ -2806,7 +2827,8 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
if (intel_port_is_combophy(dev_priv, port)) {
min = DPLL_ID_ICL_DPLL0;
max = DPLL_ID_ICL_DPLL1;
- ret = icl_calc_dpll_state(crtc_state, encoder);
+ ret = icl_calc_dpll_state(crtc_state, encoder,
+ &crtc_state->dpll_hw_state);
} else if (intel_port_is_tc(dev_priv, port)) {
if (encoder->type == INTEL_OUTPUT_DP_MST) {
struct intel_dp_mst_encoder *mst_encoder;
@@ -2820,14 +2842,16 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) {
min = DPLL_ID_ICL_TBTPLL;
max = min;
- ret = icl_calc_dpll_state(crtc_state, encoder);
+ ret = icl_calc_dpll_state(crtc_state, encoder,
+ &crtc_state->dpll_hw_state);
} else {
enum tc_port tc_port;
tc_port = intel_port_to_tc(dev_priv, port);
min = icl_tc_port_to_pll_id(tc_port);
max = min;
- ret = icl_calc_mg_pll_state(crtc_state);
+ ret = icl_calc_mg_pll_state(crtc_state,
+ &crtc_state->dpll_hw_state);
}
} else {
MISSING_CASE(port);
@@ -2840,13 +2864,17 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
}
- pll = intel_find_shared_dpll(crtc_state, min, max);
+ pll = intel_find_shared_dpll(crtc_state, &crtc_state->dpll_hw_state,
+ min, max);
if (!pll) {
DRM_DEBUG_KMS("No PLL selected\n");
return NULL;
}
- intel_reference_shared_dpll(pll, crtc_state);
+ intel_reference_shared_dpll(pll, &crtc_state->dpll_hw_state,
+ crtc_state);
+
+ crtc_state->shared_dpll = pll;
return pll;
}
--
2.17.1
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