[PATCH 4/6] drm/i915: add display register accessors

[Daniele Ceraolo Spurio]

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 57 +++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e7901890e17a..c554b7697bdc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2747,6 +2747,63 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
 
+/*
+ * The following are mmio-accessors that use an independent lock and skip all
+ * the forcewake logic, to be used to access display registers, which are
+ * outside the GT forcewake wells.
+ */
+static inline void
+intel_assert_register_is_display(struct drm_i915_private *i915, i915_reg_t reg)
+{
+#ifdef CONFIG_DRM_I915_DEBUG_MMIO
+	u32 offset = i915_mmio_reg_offset(reg);
+	bool is_de_register;
+
+	if (INTEL_GEN(i915) >= 5) {
+		is_de_register = offset >= 0x40000 &&
+			(INTEL_GEN(i915) < 11 || offset < 0x1c0000);
+	} else {
+		is_de_register =
+			(offset >= 0x5000 && offset <= 0x5fff) ||
+			(offset >= 0x6000 && offset <= 0x6fff) ||
+			(offset >= 0xa000 && offset <= 0xafff) ||
+			offset >= 0x30000;
+	}
+
+	WARN_ONCE(!is_de_register,
+		  "display reg access function used for non-display reg 0x%08x\n",
+		  offset);
+#endif
+}
+
+static inline u32
+intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
+{
+	intel_assert_register_is_display(i915, reg);
+	return intel_uncore_read(&i915->de_uncore, reg);
+}
+
+static inline void
+intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
+{
+	intel_assert_register_is_display(i915, reg);
+	intel_uncore_posting_read(&i915->de_uncore, reg);
+}
+
+static inline void
+intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
+{
+	intel_assert_register_is_display(i915, reg);
+	intel_uncore_write(&i915->de_uncore, reg, val);
+}
+
+static inline void
+intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
+{
+	intel_assert_register_is_display(i915, reg);
+	intel_uncore_rmw(&i915->de_uncore, reg, clear, set);
+}
+
 /* "Broadcast RGB" property */
 #define INTEL_BROADCAST_RGB_AUTO 0
 #define INTEL_BROADCAST_RGB_FULL 1
-- 
2.20.1