[PATCH v2] drm/i915/icl: Fix clockgating issue when using scalers

[Radhakrishna Sripada]

Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)

V2: Fix typo in headline(Chris)
    Handle the non double buffered nature of the register(Ville)

Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Cc: Aditya Swarup <aditya.swarup at intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 50 +++++++++++++++++++---------
 1 file changed, 35 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01cdd6e745c3..b9aa20ff78ea 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -469,13 +469,22 @@ static const struct intel_limit intel_limits_bxt = {
 static void
 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 {
+	u32 val = 0;
+
+	/*
+	 * Wa_2006604312:icl
+	 */
+	if (IS_ICELAKE(dev_priv))
+		val = DPFR_GATING_DIS;
+	else
+		val = DUPS1_GATING_DIS | DUPS2_GATING_DIS;
+
+	/* WA Display #0827: Gen9:all */
 	if (enable)
-		I915_WRITE(CLKGATE_DIS_PSL(pipe),
-			   DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+		I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
 	else
 		I915_WRITE(CLKGATE_DIS_PSL(pipe),
-			   I915_READ(CLKGATE_DIS_PSL(pipe)) &
-			   ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
+			   I915_READ(CLKGATE_DIS_PSL(pipe)) & ~val);
 }
 
 static bool
@@ -5203,9 +5212,17 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 static void skylake_scaler_disable(struct intel_crtc *crtc)
 {
 	int i;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	i915_reg_t reg = CLKGATE_DIS_PSL(crtc->pipe);
 
 	for (i = 0; i < crtc->num_scalers; i++)
 		skl_detach_scaler(crtc, i);
+
+	/*
+	 * Wa_2006604312:icl
+	 */
+	if (IS_ICELAKE(dev_priv))
+		I915_WRITE(reg, I915_READ(reg) & ~DPFR_GATING_DIS);
 }
 
 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -5215,6 +5232,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	const struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
+	i915_reg_t reg = CLKGATE_DIS_PSL(pipe);
 
 	if (crtc_state->pch_pfit.enabled) {
 		u16 uv_rgb_hphase, uv_rgb_vphase;
@@ -5481,14 +5499,18 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
 	return !old_crtc_state->ips_enabled;
 }
 
-static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
+static bool skl_needs_clk_wa(struct drm_i915_private *dev_priv,
 			  const struct intel_crtc_state *crtc_state)
 {
-	if (!crtc_state->nv12_planes)
-		return false;
-
 	/* WA Display #0827: Gen9:all */
-	if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
+	if (!!crtc_state->nv12_planes && IS_GEN(dev_priv, 9) &&
+	    !IS_GEMINILAKE(dev_priv))
+		return true;
+
+	/*
+	 * Wa_2006604312:icl
+	 */
+	if (IS_ICELAKE(dev_priv) && crtc_state->pch_pfit.enabled)
 		return true;
 
 	return false;
@@ -5527,9 +5549,8 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 			intel_post_enable_primary(&crtc->base, pipe_config);
 	}
 
-	/* Display WA 827 */
-	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    !needs_nv12_wa(dev_priv, pipe_config)) {
+	if (skl_needs_clk_wa(dev_priv, old_crtc_state) &&
+	    !skl_needs_clk_wa(dev_priv, pipe_config)) {
 		skl_wa_clkgate(dev_priv, crtc->pipe, false);
 	}
 }
@@ -5566,9 +5587,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 	}
 
-	/* Display WA 827 */
-	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
-	    needs_nv12_wa(dev_priv, pipe_config)) {
+	if (!skl_needs_clk_wa(dev_priv, old_crtc_state) &&
+	    skl_needs_clk_wa(dev_priv, pipe_config)) {
 		skl_wa_clkgate(dev_priv, crtc->pipe, true);
 	}
 
-- 
2.20.0.rc2.7.g965798d1f299