[PATCH 5/5] test: drm/i915: Remove fence requiremnt from FBC

[José Roberto de Souza]

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  5 ++--
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 drivers/gpu/drm/i915/intel_fbc.c     | 36 ++++++++++++----------------
 drivers/gpu/drm/i915/intel_sprite.c  |  3 +--
 4 files changed, 18 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7474e0825087..373c13187802 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2031,7 +2031,7 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 
-	return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
+	return INTEL_GEN(dev_priv) < 4;
 }
 
 struct i915_vma *
@@ -14365,8 +14365,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	plane->id = PLANE_PRIMARY;
 	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
 
-	plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
-	if (plane->has_fbc) {
+	if (i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane)) {
 		struct intel_fbc *fbc = &dev_priv->fbc;
 
 		fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cbf3b2497537..df5b90ae9e9b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1123,7 +1123,6 @@ struct intel_plane {
 	enum i9xx_plane_id i9xx_plane;
 	enum plane_id id;
 	enum pipe pipe;
-	bool has_fbc;
 	bool has_ccs;
 	u32 frontbuffer_bit;
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 20b882e72453..c843408617a6 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -249,6 +249,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 			I915_WRITE(SNB_DPFC_CTL_SA, 0);
 			I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 		}
+		DRM_DEBUG_KMS("ilk_fbc_activate() fence disabled on FBC\n");
 	}
 
 	I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
@@ -323,8 +324,9 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 			   params->vma->fence->id);
 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 	} else {
-		I915_WRITE(SNB_DPFC_CTL_SA,0);
+		I915_WRITE(SNB_DPFC_CTL_SA, 0);
 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
+		DRM_DEBUG_KMS("gen7_fbc_activate() fence disabled on FBC\n");
 	}
 
 	if (dev_priv->fbc.false_color)
@@ -689,8 +691,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 
 	cache->vma = plane_state->vma;
 	cache->flags = plane_state->flags;
-	if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
-		cache->flags &= ~PLANE_HAS_FENCE;
+	/* remove fence */
+	cache->flags &= ~PLANE_HAS_FENCE;
 }
 
 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
@@ -722,23 +724,10 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 		return false;
 	}
 
-	/* The use of a CPU fence is mandatory in order to detect writes
-	 * by the CPU to the scanout and trigger updates to the FBC.
-	 *
-	 * Note that is possible for a tiled surface to be unmappable (and
-	 * so have no fence associated with it) due to aperture constraints
-	 * at the time of pinning.
-	 *
-	 * FIXME with 90/270 degree rotation we should use the fence on
-	 * the normal GTT view (the rotated view doesn't even have a
-	 * fence). Would need changes to the FBC fence Y offset as well.
-	 * For now this will effectively disable FBC with 90/270 degree
-	 * rotation.
-	 */
 	if (!(cache->flags & PLANE_HAS_FENCE)) {
-		/* Requirements not meet see i915_gem_object_pin_to_display_plane(), __i915_vma_set_map_and_fenceable() */
-		fbc->no_fbc_reason = "framebuffer not fenced";
-		return false;
+		DRM_DEBUG_KMS("FBC plane don't have fence");
+	} else {
+		DRM_DEBUG_KMS("FBC plane have fence");
 	}
 
 	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
@@ -1046,8 +1035,13 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 		struct intel_crtc_state *crtc_state;
 		struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
 
-		if (!plane->has_fbc)
-			continue;
+		if (INTEL_GEN(dev_priv) >= 9) {
+			if (plane->pipe != PIPE_A || plane->id != PLANE_PRIMARY)
+				continue;
+		} else {
+			if (plane->i9xx_plane != PLANE_A)
+				continue;
+		}
 
 		if (!plane_state->base.visible)
 			continue;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 3f2055f70d05..518be1e06e3e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -2232,8 +2232,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	plane->id = plane_id;
 	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
 
-	plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
-	if (plane->has_fbc) {
+	if (skl_plane_has_fbc(dev_priv, pipe, plane_id)) {
 		struct intel_fbc *fbc = &dev_priv->fbc;
 
 		fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
-- 
2.21.0