[PATCH v2 26/30] drm/i915/guc: Properly capture & release GuC interrupts on Gen11

[Michal Wajdeczko]

From: Oscar Mateo <oscar.mateo at intel.com>

With the new interrupt re-partitioning in Gen11, GuC controls by itself
the interrupts it receives, so steering bits and registers have been
defeatured. Being this the case, when the GuC is in control of
submissions we won't know what to do with the ctx switch interrupt
in the driver, so disable it.

Bspec: 12609
Bspec: 10800
Bspec: 10932
Bspec: 10934
Bspec: 9517

Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: Michal Winiarski <michal.winiarski at intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c             |  2 +-
 drivers/gpu/drm/i915/intel_guc_submission.c | 57 ++++++++++++++++++++-
 2 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 455b2bf691b5..4de6474b6a25 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4634,7 +4634,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) <= 7)
 		rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11)
 		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
 	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index b0b10cac9b9b..e3f6e2b1aa99 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1263,7 +1263,7 @@ void intel_guc_submission_fini(struct intel_guc *guc)
 		guc_stage_desc_pool_destroy(guc);
 }
 
-static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
+static void gen8_guc_interrupts_capture(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	struct intel_engine_cs *engine;
@@ -1308,7 +1308,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 	rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 }
 
-static void guc_interrupts_release(struct drm_i915_private *dev_priv)
+static void gen8_guc_interrupts_release(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 	struct intel_engine_cs *engine;
@@ -1333,6 +1333,59 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
 	rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
 }
 
+static void gen11_guc_interrupts_capture(struct drm_i915_private *dev_priv)
+{
+	struct intel_rps *rps = &dev_priv->gt_pm.rps;
+	u32 tmp;
+	u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
+
+	/* Don't handle ctx switch interrupt in GuC submission mode */
+	tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+	tmp &= ~(irqs << 16 | irqs);
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp);
+
+	tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+	tmp &= ~(irqs << 16 | irqs);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp);
+
+	/* GuC needs ARAT expired interrupt unmasked */
+	rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+}
+
+static void gen11_guc_interrupts_release(struct drm_i915_private *dev_priv)
+{
+	struct intel_rps *rps = &dev_priv->gt_pm.rps;
+	u32 tmp;
+	u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
+
+	/* Handle ctx switch interrupts again */
+	tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+	tmp |= (irqs << 16 | irqs);
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp);
+
+	tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+	tmp |= (irqs << 16 | irqs);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp);
+
+	rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
+}
+
+static void guc_interrupts_capture(struct drm_i915_private *i915)
+{
+	if (INTEL_GEN(i915) >= 11)
+		gen11_guc_interrupts_capture(i915);
+	else
+		gen8_guc_interrupts_capture(i915);
+}
+
+static void guc_interrupts_release(struct drm_i915_private *i915)
+{
+	if (INTEL_GEN(i915) >= 11)
+		gen11_guc_interrupts_release(i915);
+	else
+		gen8_guc_interrupts_release(i915);
+}
+
 static void guc_submission_park(struct intel_engine_cs *engine)
 {
 	intel_engine_unpin_breadcrumbs_irq(engine);
-- 
2.19.2