[PATCH] drm/i915/perf: Use gen_mask to check supported formats

[Umesh Nerlige Ramappa]

Replace multiple instances of format arrays with one and use gen_mask to
check for supported formats.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c       | 42 +++++++++-----------------
 drivers/gpu/drm/i915/i915_perf_types.h |  1 +
 2 files changed, 16 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c380aba1ce9..51241d5b3d5a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -323,26 +323,18 @@ static u32 i915_oa_max_sample_rate = 100000;
  * code assumes all reports have a power-of-two size and ~(size - 1) can
  * be used as a mask to align the OA tail pointer.
  */
-static const struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = {
-	[I915_OA_FORMAT_A13]	    = { 0, 64 },
-	[I915_OA_FORMAT_A29]	    = { 1, 128 },
-	[I915_OA_FORMAT_A13_B8_C8]  = { 2, 128 },
+static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
+	[I915_OA_FORMAT_A13]	    = { 0, 64,  INTEL_GEN_MASK(4, 7) },
+	[I915_OA_FORMAT_A29]	    = { 1, 128, INTEL_GEN_MASK(4, 7) },
+	[I915_OA_FORMAT_A13_B8_C8]  = { 2, 128, INTEL_GEN_MASK(4, 7) },
 	/* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
-	[I915_OA_FORMAT_B4_C8]	    = { 4, 64 },
-	[I915_OA_FORMAT_A45_B8_C8]  = { 5, 256 },
-	[I915_OA_FORMAT_B4_C8_A16]  = { 6, 128 },
-	[I915_OA_FORMAT_C4_B8]	    = { 7, 64 },
-};
-
-static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
-	[I915_OA_FORMAT_A12]		    = { 0, 64 },
-	[I915_OA_FORMAT_A12_B8_C8]	    = { 2, 128 },
-	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
-	[I915_OA_FORMAT_C4_B8]		    = { 7, 64 },
-};
-
-static const struct i915_oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = {
-	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+	[I915_OA_FORMAT_B4_C8]	    = { 4, 64,  INTEL_GEN_MASK(4, 7) },
+	[I915_OA_FORMAT_A45_B8_C8]  = { 5, 256, INTEL_GEN_MASK(4, 7) },
+	[I915_OA_FORMAT_B4_C8_A16]  = { 6, 128, INTEL_GEN_MASK(4, 7) },
+	[I915_OA_FORMAT_C4_B8]	    = { 7, 64,  INTEL_GEN_MASK(4, 7) },
+	[I915_OA_FORMAT_A12]		    = { 0, 64,  INTEL_GEN_MASK(8, 11) },
+	[I915_OA_FORMAT_A12_B8_C8]	    = { 2, 128, INTEL_GEN_MASK(8, 11) },
+	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256, INTEL_GEN_MASK(8, 12) },
 };
 
 #define SAMPLE_OA_REPORT      (1<<0)
@@ -3509,7 +3501,8 @@ static int read_properties_unlocked(struct i915_perf *perf,
 					  value);
 				return -EINVAL;
 			}
-			if (!perf->oa_formats[value].size) {
+			if (INTEL_INFO(perf->i915)->gen_mask &
+			    perf->oa_formats[value].gen_mask) {
 				DRM_DEBUG("Unsupported OA report format %llu\n",
 					  value);
 				return -EINVAL;
@@ -4207,6 +4200,8 @@ void i915_perf_init(struct drm_i915_private *i915)
 
 	/* XXX const struct i915_perf_ops! */
 
+	perf->oa_formats = oa_formats;
+
 	if (IS_HASWELL(i915)) {
 		perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
 		perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
@@ -4218,7 +4213,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 		perf->ops.read = gen7_oa_read;
 		perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
 
-		perf->oa_formats = hsw_oa_formats;
 	} else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
 		/* Note: that although we could theoretically also support the
 		 * legacy ringbuffer mode on BDW (and earlier iterations of
@@ -4229,8 +4223,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 		perf->ops.read = gen8_oa_read;
 
 		if (IS_GEN_RANGE(i915, 8, 9)) {
-			perf->oa_formats = gen8_plus_oa_formats;
-
 			perf->ops.is_valid_b_counter_reg =
 				gen7_is_valid_b_counter_addr;
 			perf->ops.is_valid_mux_reg =
@@ -4261,8 +4253,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 				perf->gen8_valid_ctx_bit = BIT(16);
 			}
 		} else if (IS_GEN_RANGE(i915, 10, 11)) {
-			perf->oa_formats = gen8_plus_oa_formats;
-
 			perf->ops.is_valid_b_counter_reg =
 				gen7_is_valid_b_counter_addr;
 			perf->ops.is_valid_mux_reg =
@@ -4285,8 +4275,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 			}
 			perf->gen8_valid_ctx_bit = BIT(16);
 		} else if (IS_GEN(i915, 12)) {
-			perf->oa_formats = gen12_oa_formats;
-
 			perf->ops.is_valid_b_counter_reg =
 				gen12_is_valid_b_counter_addr;
 			perf->ops.is_valid_mux_reg =
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 74ddc20a0d37..0e2fd724861c 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -30,6 +30,7 @@ struct intel_engine_cs;
 struct i915_oa_format {
 	u32 format;
 	int size;
+	u32 gen_mask;
 };
 
 struct i915_oa_reg {
-- 
2.20.1