[PATCH 3/3] alignment
Matthew Auld
matthew.auld at intel.com
Sat Nov 9 16:10:21 UTC 2019
[63429.629389] perf_huge_copy_blt src(S ps 1000) -> dst(S ps 1000): 16384 KiB copy: 15334 MiB/s
[63429.634784] perf_huge_copy_blt src(S ps 1000) -> dst(S ps 10000): 16384 KiB copy: 15584 MiB/s
[63429.640189] perf_huge_copy_blt src(S ps 1000) -> dst(S ps 200000): 16384 KiB copy: 15296 MiB/s
[63429.645846] perf_huge_copy_blt src(S ps 10000) -> dst(S ps 1000): 16384 KiB copy: 15747 MiB/s
[63429.651271] perf_huge_copy_blt src(S ps 10000) -> dst(S ps 10000): 16384 KiB copy: 15161 MiB/s
[63429.656652] perf_huge_copy_blt src(S ps 10000) -> dst(S ps 200000): 16384 KiB copy: 15257 MiB/s
[63429.662732] perf_huge_copy_blt src(S ps 200000) -> dst(S ps 1000): 16384 KiB copy: 13949 MiB/s
[63429.668235] perf_huge_copy_blt src(S ps 200000) -> dst(S ps 10000): 16384 KiB copy: 15042 MiB/s
[63429.674084] perf_huge_copy_blt src(S ps 200000) -> dst(S ps 200000): 16384 KiB copy: 14023 MiB/s
[63429.682165] perf_huge_copy_blt src(S ps 1000) -> dst(L ps 1000): 16384 KiB copy: 13718 MiB/s
[63429.688224] perf_huge_copy_blt src(S ps 1000) -> dst(L ps 10000): 16384 KiB copy: 14131 MiB/s
[63429.694270] perf_huge_copy_blt src(S ps 1000) -> dst(L ps 200000): 16384 KiB copy: 13881 MiB/s
[63429.700357] perf_huge_copy_blt src(S ps 10000) -> dst(L ps 1000): 16384 KiB copy: 14245 MiB/s
[63429.706506] perf_huge_copy_blt src(S ps 10000) -> dst(L ps 10000): 16384 KiB copy: 13947 MiB/s
[63429.712219] perf_huge_copy_blt src(S ps 10000) -> dst(L ps 200000): 16384 KiB copy: 14569 MiB/s
[63429.718428] perf_huge_copy_blt src(S ps 200000) -> dst(L ps 1000): 16384 KiB copy: 13995 MiB/s
[63429.724489] perf_huge_copy_blt src(S ps 200000) -> dst(L ps 10000): 16384 KiB copy: 13934 MiB/s
[63429.730375] perf_huge_copy_blt src(S ps 200000) -> dst(L ps 200000): 16384 KiB copy: 14214 MiB/s
[63429.741029] perf_huge_copy_blt src(L ps 1000) -> dst(S ps 1000): 16384 KiB copy: 11920 MiB/s
[63429.747406] perf_huge_copy_blt src(L ps 1000) -> dst(S ps 10000): 16384 KiB copy: 13197 MiB/s
[63429.753927] perf_huge_copy_blt src(L ps 1000) -> dst(S ps 200000): 16384 KiB copy: 12764 MiB/s
[63429.760506] perf_huge_copy_blt src(L ps 10000) -> dst(S ps 1000): 16384 KiB copy: 13204 MiB/s
[63429.767192] perf_huge_copy_blt src(L ps 10000) -> dst(S ps 10000): 16384 KiB copy: 12921 MiB/s
[63429.773442] perf_huge_copy_blt src(L ps 10000) -> dst(S ps 200000): 16384 KiB copy: 13243 MiB/s
[63429.779993] perf_huge_copy_blt src(L ps 200000) -> dst(S ps 1000): 16384 KiB copy: 13138 MiB/s
[63429.786500] perf_huge_copy_blt src(L ps 200000) -> dst(S ps 10000): 16384 KiB copy: 12854 MiB/s
[63429.793253] perf_huge_copy_blt src(L ps 200000) -> dst(S ps 200000): 16384 KiB copy: 12700 MiB/s
[63429.804161] perf_huge_copy_blt src(L ps 1000) -> dst(L ps 1000): 16384 KiB copy: 8679 MiB/s
[63429.814767] perf_huge_copy_blt src(L ps 1000) -> dst(L ps 10000): 16384 KiB copy: 7602 MiB/s
[63429.824274] perf_huge_copy_blt src(L ps 1000) -> dst(L ps 200000): 16384 KiB copy: 8591 MiB/s
[63429.834000] perf_huge_copy_blt src(L ps 10000) -> dst(L ps 1000): 16384 KiB copy: 8712 MiB/s
[63429.844682] perf_huge_copy_blt src(L ps 10000) -> dst(L ps 10000): 16384 KiB copy: 7555 MiB/s
[63429.853870] perf_huge_copy_blt src(L ps 10000) -> dst(L ps 200000): 16384 KiB copy: 8855 MiB/s
[63429.863474] perf_huge_copy_blt src(L ps 200000) -> dst(L ps 1000): 16384 KiB copy: 8911 MiB/s
[63429.873676] perf_huge_copy_blt src(L ps 200000) -> dst(L ps 10000): 16384 KiB copy: 8418 MiB/s
[63429.882826] perf_huge_copy_blt src(L ps 200000) -> dst(L ps 200000): 16384 KiB copy: 8985 MiB/s
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 -
.../gpu/drm/i915/gem/selftests/huge_pages.c | 460 +++++++++++++++++-
drivers/gpu/drm/i915/i915_pci.c | 5 +-
drivers/gpu/drm/i915/intel_memory_region.h | 2 +
4 files changed, 461 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 15f8297dc34e..5c39d878cd6d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -214,8 +214,6 @@ struct drm_i915_gem_object {
unsigned int gtt;
} page_sizes;
- I915_SELFTEST_DECLARE(unsigned int page_mask);
-
struct i915_gem_object_page_iter {
struct scatterlist *sg_pos;
unsigned int sg_idx; /* in pages, but 32bit eek! */
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a1aab82b37ba..d1e6dfdd139f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -4,15 +4,19 @@
* Copyright © 2017 Intel Corporation
*/
+#include <linux/sort.h>
#include <linux/prime_numbers.h>
#include "i915_selftest.h"
+#include "gem/i915_gem_object_blt.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
+#include "gt/intel_rps.h"
#include "igt_gem_utils.h"
#include "mock_context.h"
@@ -56,13 +60,17 @@ static void huge_pages_free_pages(struct sg_table *st)
kfree(st);
}
+#define I915_BO_ALLOC_TRANSHUGE BIT(9)
+
static int get_huge_pages(struct drm_i915_gem_object *obj)
{
#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)
- unsigned int page_mask = obj->mm.page_mask;
+ unsigned int flags_mask = obj->flags & PAGE_MASK;
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
+ unsigned int page_mask;
+ gfp_t gfp;
u64 rem;
st = kmalloc(sizeof(*st), GFP);
@@ -74,11 +82,22 @@ static int get_huge_pages(struct drm_i915_gem_object *obj)
return -ENOMEM;
}
+ page_mask = flags_mask;
rem = obj->base.size;
sg = st->sgl;
st->nents = 0;
sg_page_sizes = 0;
+ gfp = GFP | __GFP_ZERO;
+ if (obj->flags & I915_BO_ALLOC_TRANSHUGE) {
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+ GEM_BUG_ON(!IS_ALIGNED(rem, HPAGE_PMD_SIZE));
+ gfp = GFP_TRANSHUGE_LIGHT | GFP_HIGHUSER_MOVABLE | __GFP_ZERO;
+#else
+ GEM_BUG_ON(1);
+#endif
+ }
+
/*
* Our goal here is simple, we want to greedily fill the object from
* largest to smallest page-size, while ensuring that we use *every*
@@ -93,7 +112,7 @@ static int get_huge_pages(struct drm_i915_gem_object *obj)
struct page *page;
GEM_BUG_ON(order >= MAX_ORDER);
- page = alloc_pages(GFP | __GFP_ZERO, order);
+ page = alloc_pages(gfp, order);
if (!page)
goto err;
@@ -116,7 +135,7 @@ static int get_huge_pages(struct drm_i915_gem_object *obj)
if (i915_gem_gtt_prepare_pages(obj, st))
goto err;
- GEM_BUG_ON(sg_page_sizes != obj->mm.page_mask);
+ GEM_BUG_ON(sg_page_sizes != flags_mask);
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
@@ -148,10 +167,11 @@ static const struct drm_i915_gem_object_ops huge_page_ops = {
static struct drm_i915_gem_object *
huge_pages_object(struct drm_i915_private *i915,
u64 size,
- unsigned int page_mask)
+ unsigned int flags)
{
static struct lock_class_key lock_class;
struct drm_i915_gem_object *obj;
+ unsigned int page_mask = flags & PAGE_MASK;
GEM_BUG_ON(!size);
GEM_BUG_ON(!IS_ALIGNED(size, BIT(__ffs(page_mask))));
@@ -175,7 +195,7 @@ huge_pages_object(struct drm_i915_private *i915,
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->cache_level = I915_CACHE_NONE;
- obj->mm.page_mask = page_mask;
+ obj->flags |= flags;
return obj;
}
@@ -1410,6 +1430,12 @@ igt_create_system(struct drm_i915_private *i915, u32 size, u32 flags)
return huge_pages_object(i915, size, size);
}
+static struct drm_i915_gem_object *
+igt_create_system_mask(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+ return huge_pages_object(i915, size, flags);
+}
+
static struct drm_i915_gem_object *
igt_create_local(struct drm_i915_private *i915, u32 size, u32 flags)
{
@@ -1914,6 +1940,427 @@ static int igt_shrink_thp(void *arg)
return err;
}
+static void perf_begin(struct intel_gt *gt)
+{
+ intel_gt_pm_get(gt);
+
+ /* Boost gpufreq to max [waitboost] and keep it fixed */
+ atomic_inc(>->rps.num_waiters);
+ schedule_work(>->rps.work);
+ flush_work(>->rps.work);
+}
+
+static void perf_end(struct intel_gt *gt)
+{
+ atomic_dec(>->rps.num_waiters);
+ intel_gt_pm_put(gt);
+}
+
+static int wrap_ktime_compare(const void *A, const void *B)
+{
+ const ktime_t *a = A, *b = B;
+
+ return ktime_compare(*a, *b);
+}
+
+static int perf_measure_fill(struct intel_context *ce,
+ struct drm_i915_gem_object *obj,
+ u64 *bw)
+{
+ ktime_t t[5];
+ int i, err;
+
+ for (i = 0; i < ARRAY_SIZE(t); ++i) {
+ ktime_t t0, t1;
+
+ t0 = ktime_get();
+
+ err = i915_gem_object_fill_blt(obj, ce, 0xdeadbeaf);
+ if (err)
+ break;
+
+ err = i915_gem_object_wait(obj,
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ break;
+
+ t1 = ktime_get();
+ t[i] = ktime_sub(t1, t0);
+ }
+
+ sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ *bw = div64_u64(mul_u32_u32(4 * obj->base.size,
+ 1000 * 1000 * 1000),
+ t[1] + 2 * t[2] + t[3]) >> 20;
+
+ return err;
+}
+
+static int perf_huge_fill_blt(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct drm_i915_gem_object *obj;
+ struct intel_gt *gt = &i915->gt;
+ const unsigned int size = SZ_16M;
+ struct {
+ igt_create_fn fn;
+ unsigned int flags;
+ const char *name;
+ } backends[] = {
+ { igt_create_system_mask, SZ_2M, "S" },
+ { igt_create_local, I915_BO_ALLOC_CONTIGUOUS, "L" },
+ };
+ int bit, max, i;
+ int err;
+ u64 bw;
+
+ if (supported == SZ_4K)
+ return 0;
+
+ perf_begin(gt);
+
+ for (i = 0; i < ARRAY_SIZE(backends); ++i) {
+ obj = backends[i].fn(i915, size, backends[i].flags);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -ENODEV) {
+ err = 0;
+ continue;
+ }
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ max = ilog2(SZ_2M) + 1;
+
+ for_each_set_bit(bit, &supported, max) {
+ unsigned int page_size = BIT(bit);
+
+ obj->mm.page_sizes.sg = page_size;
+
+ err = perf_measure_fill(ce, obj, &bw);
+ if (err)
+ break;
+
+ pr_info("%s fill(%s ps %6x): %zd KiB fill: %lld MiB/s\n",
+ __func__, backends[i].name, page_size,
+ obj->base.size >> 10, bw);
+
+ err = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ if (err)
+ break;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err)
+ break;
+ }
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ perf_end(gt);
+ return err;
+}
+
+static int perf_measure_copy(struct intel_context *ce,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ u64 *bw)
+{
+ ktime_t t[5];
+ int i, err;
+
+ for (i = 0; i < ARRAY_SIZE(t); ++i) {
+ ktime_t t0, t1;
+
+ t0 = ktime_get();
+
+ err = i915_gem_object_copy_blt(src, dst, ce);
+ if (err)
+ break;
+
+ err = i915_gem_object_wait(dst,
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ break;
+
+ t1 = ktime_get();
+ t[i] = ktime_sub(t1, t0);
+ }
+
+ sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ *bw = div64_u64(mul_u32_u32(4 * src->base.size,
+ 1000 * 1000 * 1000),
+ t[1] + 2 * t[2] + t[3]) >> 20;
+
+ return err;
+}
+
+static int perf_huge_copy_blt(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ unsigned long supported = INTEL_INFO(i915)->page_sizes;
+ struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct drm_i915_gem_object *src, *dst;
+ struct intel_gt *gt = &i915->gt;
+ const unsigned int size = SZ_16M;
+ struct {
+ igt_create_fn fn;
+ unsigned int flags;
+ const char *name;
+ } backends[] = {
+ { igt_create_system_mask, SZ_2M, "S" },
+ { igt_create_local, I915_BO_ALLOC_CONTIGUOUS, "L" },
+ };
+ int src_bit, dst_bit;
+ int err, max, i, j;
+ u64 bw;
+
+ if (supported == SZ_4K)
+ return 0;
+
+ perf_begin(gt);
+
+ max = ilog2(SZ_2M) + 1;
+
+ for (i = 0; i < ARRAY_SIZE(backends); ++i) {
+ src = backends[i].fn(i915, size, backends[i].flags);
+ if (IS_ERR(src)) {
+ err = PTR_ERR(dst);
+ if (err == -ENODEV) {
+ err = 0;
+ continue;
+ }
+
+ goto out_end;
+ }
+
+ err = i915_gem_object_pin_pages(src);
+ if (err)
+ goto out_put_src;
+
+ for (j = 0; j < ARRAY_SIZE(backends); ++j) {
+ dst = backends[j].fn(i915, size, backends[j].flags);
+ if (IS_ERR(dst)) {
+ err = PTR_ERR(dst);
+ if (err == -ENODEV) {
+ err = 0;
+ continue;
+ }
+
+ goto out_unpin_src;
+ }
+
+ err = i915_gem_object_pin_pages(dst);
+ if (err)
+ goto out_put_dst;
+
+ for_each_set_bit(src_bit, &supported, max) {
+ unsigned int src_page_size = BIT(src_bit);
+
+ src->mm.page_sizes.sg = src_page_size;
+
+ for_each_set_bit(dst_bit, &supported, max) {
+ unsigned int dst_page_size = BIT(dst_bit);
+
+ dst->mm.page_sizes.sg = dst_page_size;
+
+ err = perf_measure_copy(ce, src, dst, &bw);
+ if (err)
+ goto out_unpin_dst;
+
+ pr_info("%s src(%s ps %6x) -> dst(%s ps %6x): %zd KiB copy: %llu MiB/s\n",
+ __func__,
+ backends[i].name,
+ src_page_size,
+ backends[j].name,
+ dst_page_size,
+ src->base.size >> 10,
+ bw);
+
+ err = i915_gem_object_unbind(dst, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ if (err)
+ goto out_unpin_dst;
+ }
+
+ err = i915_gem_object_unbind(src, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ if (err)
+ goto out_unpin_dst;
+
+ cond_resched();
+ }
+out_unpin_dst:
+ i915_gem_object_unpin_pages(dst);
+out_put_dst:
+ i915_gem_object_put(dst);
+
+ if (err)
+ break;
+ }
+out_unpin_src:
+ i915_gem_object_unpin_pages(src);
+out_put_src:
+ i915_gem_object_put(src);
+
+ if (err)
+ break;
+ }
+
+out_end:
+ if (err == -ENOMEM)
+ err = 0;
+
+ perf_end(gt);
+ return err;
+}
+
+static struct intel_memory_region *
+igt_create_stolen_region(struct drm_i915_private *i915, u32 min_size)
+{
+ struct intel_memory_region *mem;
+ struct drm_i915_gem_object *obj;
+ resource_size_t start;
+ u64 chunk;
+
+ chunk = SZ_128M;
+ do {
+ obj = i915_gem_object_create_stolen(i915, chunk);
+ if (!IS_ERR(obj))
+ break;
+
+ chunk >>= 1;
+ } while (chunk >= min_size);
+
+ if (chunk < min_size)
+ return ERR_PTR(-ENOSPC);
+
+ start = i915_gem_object_get_dma_address(obj, 0);
+
+ pr_info("chunk=%llu\n", chunk);
+ pr_info("start=%llu\n", (u64)start);
+
+ mem = mock_region_create(i915, start, chunk, SZ_2M, 0);
+ if (IS_ERR(mem)) {
+ i915_gem_object_put(obj);
+ return mem;
+ }
+
+ mem->private = obj;
+ return mem;
+}
+
+void igt_destroy_stolen_region(struct intel_memory_region *mem)
+{
+ struct drm_i915_gem_object *obj = mem->private;
+
+ i915_gem_object_put(obj);
+ intel_memory_region_put(mem);
+}
+
+struct intel_memory_region *igt_region;
+
+static struct drm_i915_gem_object *
+igt_create_region(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+ return i915_gem_object_create_region(igt_region, size, flags);
+}
+
+static int perf_pathological_alignment(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct drm_i915_gem_object *src, *dst;
+ struct intel_gt *gt = &i915->gt;
+ const unsigned int size = SZ_16M;
+ struct {
+ const char *name;
+ igt_create_fn fn;
+ unsigned int flags;
+ } backends[] = {
+ { "R", igt_create_region, I915_BO_ALLOC_CONTIGUOUS },
+ { "4", igt_create_system_mask, SZ_4K },
+ { "2", igt_create_system_mask, SZ_2M },
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+ { "T", igt_create_system_mask, HPAGE_PMD_SIZE | I915_BO_ALLOC_TRANSHUGE },
+#endif
+ };
+ int err;
+ int i;
+ u64 bw;
+
+ igt_region = igt_create_stolen_region(i915, size << 1);
+ if (IS_ERR(igt_region))
+ return PTR_ERR(igt_region);
+
+ perf_begin(gt);
+
+ for (i = 0; i < ARRAY_SIZE(backends); ++i) {
+ src = backends[i].fn(i915, size, backends[i].flags);
+ if (IS_ERR(src)) {
+ err = PTR_ERR(src);
+ goto out_end;
+ }
+
+ err = i915_gem_object_pin_pages(src);
+ if (err)
+ goto out_put_src;
+
+ src->mm.page_sizes.sg = SZ_4K;
+
+ dst = backends[i].fn(i915, size, backends[i].flags);
+ if (IS_ERR(dst)) {
+ err = PTR_ERR(dst);
+ goto out_unpin_src;
+ }
+
+ err = i915_gem_object_pin_pages(dst);
+ if (err)
+ goto out_put_dst;
+
+ dst->mm.page_sizes.sg = SZ_4K;
+
+ err = perf_measure_copy(ce, src, dst, &bw);
+ if (err)
+ goto out_unpin_dst;
+
+ pr_info("%s (%s) %zd KiB copy: %lld MiB/s\n",
+ __func__, backends[i].name, src->base.size >> 10, bw);
+
+out_unpin_dst:
+ i915_gem_object_unpin_pages(dst);
+out_put_dst:
+ i915_gem_object_put(dst);
+out_unpin_src:
+ i915_gem_object_unpin_pages(src);
+out_put_src:
+ i915_gem_object_put(src);
+
+ if (err)
+ break;
+ }
+
+ if (err == -ENOMEM)
+ err = 0;
+out_end:
+ igt_destroy_stolen_region(igt_region);
+
+ perf_end(gt);
+ return err;
+}
+
int i915_gem_huge_page_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
@@ -1973,6 +2420,9 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ppgtt_exhaust_huge),
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
+ SUBTEST(perf_huge_fill_blt),
+ SUBTEST(perf_huge_copy_blt),
+ SUBTEST(perf_pathological_alignment),
};
struct i915_gem_context *ctx;
struct i915_address_space *vm;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1bb701d32a5d..76fa43e41142 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -548,6 +548,8 @@ static const struct intel_device_info intel_haswell_gt3_info = {
#define BDW_PLATFORM \
GEN8_FEATURES, \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_2M, \
PLATFORM(INTEL_BROADWELL)
static const struct intel_device_info intel_broadwell_gt1_info = {
@@ -603,7 +605,8 @@ static const struct intel_device_info intel_cherryview_info = {
#define GEN9_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_64K
+ I915_GTT_PAGE_SIZE_64K | \
+ I915_GTT_PAGE_SIZE_2M
#define GEN9_FEATURES \
GEN8_FEATURES, \
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 238722009677..7fa1448dc9f5 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -69,6 +69,8 @@ struct intel_memory_region {
const struct intel_memory_region_ops *ops;
+ void *private;
+
struct io_mapping iomap;
struct resource region;
--
2.20.1
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