[PATCH 5/5] squash

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a1787d165467..87bd5c7a54aa 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2384,28 +2384,27 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 			dev_priv->max_cdclk_freq = 652800;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		dev_priv->max_cdclk_freq = 528000;
-	} else if (IS_BROXTON(dev_priv)) {
-		u32 limit = I915_READ(SKL_DFSM) & BXT_DFSM_CDCLK_LIMIT_MASK;
-		int max_cdclk, vco;
+	} else if (IS_GEN9_BC(dev_priv)) {
+		int vco;
 
 		vco = dev_priv->skl_preferred_vco_freq;
 		WARN_ON(vco != 8100000 && vco != 8640000);
 
-		/*
-		 * Use the lower (vco 8640) cdclk values as a
-		 * first guess. skl_calc_cdclk() will correct it
-		 * if the preferred vco is 8100 instead.
-		 */
+		dev_priv->max_cdclk_freq = skl_calc_cdclk(675000, vco);
+	} else if (IS_BROXTON(dev_priv)) {
+		u32 limit = I915_READ(SKL_DFSM) & BXT_DFSM_CDCLK_LIMIT_MASK;
+		int max_cdclk;
+
 		if (limit == BXT_DFSM_CDCLK_LIMIT_675)
-			max_cdclk = 617143;
+			max_cdclk = 675000;
 		else if (limit == BXT_DFSM_CDCLK_LIMIT_540)
 			max_cdclk = 540000;
 		else if (limit == BXT_DFSM_CDCLK_LIMIT_450)
-			max_cdclk = 432000;
+			max_cdclk = 540000;
 		else
-			max_cdclk = 308571;
+			max_cdclk = 337500;
 
-		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+		dev_priv->max_cdclk_freq = max_cdclk;
 	} else if (IS_GEMINILAKE(dev_priv)) {
 		dev_priv->max_cdclk_freq = 316800;
 	} else if (IS_BROADWELL(dev_priv))  {
-- 
2.23.0