[PATCH 2/3] drm/i915: Add support for scaling filters
Shashank Sharma
shashank.sharma at intel.com
Mon Oct 14 07:48:41 UTC 2019
This patch does the following:
- Creates a new property for scaling filter mode.
- Applies the chosen filter value while enabling the panel fitter.
PS: The checkpatch 80 char warnings are delibrately ignored, in favor
of better readability.
Signed-off-by: Shashank Sharma <shashank.sharma at intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 53 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++++
3 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1a533ccdb54f..9b015b9409ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5615,11 +5615,35 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
skl_detach_scaler(crtc, i);
}
+static u32
+icelake_get_scaler_filter(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_crtc_state *state = &crtc_state->base;
+
+ switch (state->scaling_filter) {
+ case DRM_SCALING_FILTER_BILINEAR:
+ return PS_FILTER_BILINEAR;
+ case DRM_SCALING_FILTER_EDGE_ENHANCE:
+ return PS_FILTER_EDGE_ENHANCE;
+ case DRM_SCALING_FILTER_NN:
+ case DRM_SCALING_FILTER_NN_IS_ONLY:
+ return PS_FILTER_PROGRAMMED;
+ case DRM_SCALING_FILTER_INVALID:
+ DRM_ERROR("Ignoring invalid scaler filter mode\n");
+ return PS_FILTER_MEDIUM;
+ case DRM_SCALING_FILTER_DEFAULT:
+ case DRM_SCALING_FILTER_MEDIUM:
+ default:
+ return PS_FILTER_MEDIUM;
+ }
+}
+
static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
+ u32 scaler_filter;
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
@@ -5640,9 +5664,11 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
+ scaler_filter = icelake_get_scaler_filter(crtc_state);
+
id = scaler_state->scaler_id;
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
- PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+ scaler_filter | scaler_state->scalers[id].mode);
I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
@@ -14996,6 +15022,29 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
return ERR_PTR(ret);
}
+static void intel_create_scaler_filter_property(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_property *prop;
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ u8 size;
+
+ if (mode_config->scaling_filter_property)
+ return;
+
+ size = ARRAY_SIZE(drm_scaling_filter_enum_list);
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
+ "SCALING_FILTERS",
+ drm_scaling_filter_enum_list, size);
+ if (!prop) {
+ DRM_ERROR("Failed to create scaling filter property\n");
+ return;
+ }
+
+ dev->mode_config.scaling_filter_property = prop;
+}
+
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
@@ -15016,6 +15065,8 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
}
scaler_state->scaler_id = -1;
+
+ intel_create_scaler_filter_property(crtc, crtc_state);
}
#define INTEL_CRTC_FUNCS \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..8da499031bc2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -620,6 +620,9 @@ struct intel_crtc_scaler_state {
/* scaler used by crtc for panel fitting purpose */
int scaler_id;
+
+ /* indicate if scaling ratio is integer, to apply scaling filters */
+ bool integer_scaling;
};
/* drm_mode->private_flags */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc067fc57ab..f1ed5aa96ffd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7114,6 +7114,7 @@ enum {
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
#define PS_FILTER_MEDIUM (0 << 23)
+#define PS_FILTER_PROGRAMMED (1 << 23)
#define PS_FILTER_EDGE_ENHANCE (2 << 23)
#define PS_FILTER_BILINEAR (3 << 23)
#define PS_VERT3TAP (1 << 21)
@@ -7190,6 +7191,24 @@ enum {
#define _PS_ECC_STAT_2B 0x68AD0
#define _PS_ECC_STAT_1C 0x691D0
+#define _PS_COEF_SET0_INDEX_1A 0x68198
+#define _PS_COEF_SET0_INDEX_2A 0x68298
+#define _PS_COEF_SET0_INDEX_1B 0x68998
+#define _PS_COEF_SET0_INDEX_2B 0x68A98
+#define _PS_COEF_SET1_INDEX_1A 0x681A0
+#define _PS_COEF_SET1_INDEX_2A 0x682A0
+#define _PS_COEF_SET1_INDEX_1B 0x689A0
+#define _PS_COEF_SET1_INDEX_2B 0x68AA0
+
+#define _PS_COEF_SET0_DATA_1A 0x6819C
+#define _PS_COEF_SET0_DATA_2A 0x6829C
+#define _PS_COEF_SET0_DATA_1B 0x6899C
+#define _PS_COEF_SET0_DATA_2B 0x68A9C
+#define _PS_COEF_SET1_DATA_1A 0x681A4
+#define _PS_COEF_SET1_DATA_2A 0x682A4
+#define _PS_COEF_SET1_DATA_1B 0x689A4
+#define _PS_COEF_SET1_DATA_2B 0x68AA4
+
#define _ID(id, a, b) _PICK_EVEN(id, a, b)
#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
_ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
@@ -7218,6 +7237,18 @@ enum {
#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+#define SKL_PS_COEF_DATA_SET0(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A), \
+ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_1B))
+#define SKL_PS_COEF_DATA_SET1(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET1_DATA_1A, _PS_COEF_SET1_DATA_2A), \
+ _ID(id, _PS_COEF_SET1_DATA_1B, _PS_COEF_SET1_DATA_1B))
+#define SKL_PS_COEF_INDEX_SET0(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A), \
+ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_1B))
+#define SKL_PS_COEF_INDEX_SET1(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET1_INDEX_1A, _PS_COEF_SET1_INDEX_2A), \
+ _ID(id, _PS_COEF_SET1_INDEX_1B, _PS_COEF_SET1_INDEX_1B))
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
--
2.17.1
More information about the Intel-gfx-trybot
mailing list