[PATCH 2/2] test: drm/i915/dp/tgl: Enable clock gating

[José Roberto de Souza]

The previous patch "drm/i915/tc: Clear DKL_TX_PMD_LANE_SUS before
program voltage swing" fixed the training failures when enabling
clock gating.

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d611dc19fea0..d7d3d4137f56 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3506,13 +3506,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
 		intel_dp_stop_link_train(intel_dp);
 
 	/*
-	 * TODO: enable clock gating
-	 *
 	 * It is not written in DP enabling sequence but "PHY Clockgating
 	 * programming" states that clock gating should be enabled after the
-	 * link training but doing so causes all the following trainings to fail
-	 * so not enabling it for now.
+	 * link training
 	 */
+	icl_phy_set_clock_gating(dig_port, true);
 
 	/* 7.l */
 	intel_ddi_enable_fec(encoder, crtc_state);
-- 
2.23.0