[PATCH] live-cs-tlb
Chris Wilson
chris at chris-wilson.co.uk
Sat Sep 14 20:08:02 UTC 2019
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 242 ++++++++++++++++++
1 file changed, 242 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 598c18d10640..1a048f650215 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -25,7 +25,9 @@
#include <linux/list_sort.h>
#include <linux/prime_numbers.h>
+#include "gem/i915_gem_context.h"
#include "gem/selftests/mock_context.h"
+#include "gt/intel_context.h"
#include "i915_random.h"
#include "i915_selftest.h"
@@ -1705,6 +1707,245 @@ int i915_gem_gtt_mock_selftests(void)
return err;
}
+static int context_sync(struct intel_context *ce)
+{
+ struct i915_request *rq;
+ long timeout;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ timeout = i915_request_wait(rq, 0, HZ / 5);
+ i915_request_put(rq);
+
+ return timeout < 0 ? -EIO : 0;
+}
+
+static int igt_cs_tlb(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *bbe, *act, *out;
+ struct i915_gem_engines_iter it;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct drm_file *file;
+ struct i915_vma *vma;
+ u32 *vaddr;
+ int err = 0;
+ int i;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ mutex_lock(&i915->drm.struct_mutex);
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_unlock;
+ }
+
+ if (!ctx->vm)
+ goto out_unlock;
+
+ /* Create two pages; dummy we prefill the TLB, and intended */
+ bbe = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(bbe)) {
+ err = PTR_ERR(bbe);
+ goto out_unlock;
+ }
+
+ vaddr = i915_gem_object_pin_map(bbe, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto out_bbe;
+ }
+ memset32(vaddr, MI_BATCH_BUFFER_END, PAGE_SIZE / sizeof(u32));
+ i915_gem_object_flush_map(bbe);
+ i915_gem_object_unpin_map(bbe);
+
+ act = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(act)) {
+ err = PTR_ERR(act);
+ goto out_bbe;
+ }
+
+ vaddr = i915_gem_object_pin_map(act, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto out_act;
+ }
+ for (i = 0; i < PAGE_SIZE / 64; i++) {
+ u32 *cs = vaddr + i * 64 / sizeof(u32);
+ u64 addr = (ctx->vm->total - PAGE_SIZE) + i * sizeof(u32);
+
+ if (INTEL_GEN(i915) >= 8) {
+ cs[0]= MI_STORE_DWORD_IMM_GEN4;
+ cs[1]= lower_32_bits(addr);
+ cs[2]= upper_32_bits(addr);
+ cs[3]= i;
+ } else {
+ cs[0] = MI_STORE_DWORD_IMM_GEN4;
+ cs[1] = 0;
+ cs[2] = lower_32_bits(addr);
+ cs[3] = i;
+ }
+ cs[4] = MI_BATCH_BUFFER_END;
+ }
+ i915_gem_object_flush_map(act);
+ i915_gem_object_unpin_map(act);
+
+ out = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(out)) {
+ err = PTR_ERR(out);
+ goto out_act;
+ }
+
+ vma = i915_vma_instance(out, ctx->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_act;
+ }
+
+ err = i915_vma_pin(vma, 0, 0,
+ PIN_USER |
+ PIN_OFFSET_FIXED |
+ (ctx->vm->total - PAGE_SIZE));
+ if (err)
+ goto out_out;
+
+ vaddr = i915_gem_object_pin_map(out, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto out_out;
+ }
+
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ struct i915_request *rq;
+ u64 offset;
+
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ offset = random_offset(0,
+ ctx->vm->total - PAGE_SIZE,
+ PAGE_SIZE / 64 * PAGE_SIZE,
+ PAGE_SIZE);
+
+ err = ctx->vm->allocate_va_range(ctx->vm, offset,
+ PAGE_SIZE / 64 * PAGE_SIZE);
+ if (err)
+ break;
+
+ memset32(vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
+ i915_gem_object_flush_map(out);
+
+ vma = i915_vma_instance(bbe, ctx->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ break;
+ }
+
+ err = vma->ops->set_pages(vma);
+ if (err)
+ break;
+
+ /* Prime the TLB with the dummy pages */
+ for (i = 0; i < PAGE_SIZE / 64; i++) {
+ vma->node.start = offset + i * PAGE_SIZE;
+ ctx->vm->insert_entries(ctx->vm, vma,
+ I915_CACHE_NONE, 0);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto end;
+ }
+
+ err = rq->engine->emit_bb_start(rq,
+ vma->node.start,
+ PAGE_SIZE,
+ 0);
+ i915_request_add(rq);
+ if (err)
+ goto end;
+ }
+
+ vma->ops->clear_pages(vma);
+
+ err = context_sync(ce);
+ if (err)
+ goto end;
+
+ vma = i915_vma_instance(act, ctx->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ break;
+ }
+
+ err = vma->ops->set_pages(vma);
+ if (err)
+ break;
+
+ /* Replace the TLB with target batches */
+ for (i = 0; i < PAGE_SIZE / 64; i++) {
+ vma->node.start = offset + i * PAGE_SIZE;
+ ctx->vm->insert_entries(ctx->vm, vma,
+ I915_CACHE_NONE, 0);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto end;
+ }
+
+ err = rq->engine->emit_bb_start(rq,
+ vma->node.start +
+ i * 64,
+ PAGE_SIZE,
+ 0);
+ i915_request_add(rq);
+ if (err)
+ goto end;
+ }
+
+ err = context_sync(ce);
+ if (err)
+ goto end;
+
+ for (i = 0; i < PAGE_SIZE / 64; i++) {
+ if (vaddr[i] != i) {
+ pr_err("Write lost at offset %d, found %x, expected %x\n",
+ i, vaddr[i], i);
+ err = -EINVAL;
+ goto end;
+ }
+ }
+
+ vma->ops->clear_pages(vma);
+
+ ctx->vm->clear_range(ctx->vm,
+ offset, PAGE_SIZE / 64 * PAGE_SIZE);
+ }
+end:
+ i915_gem_context_unlock_engines(ctx);
+ i915_gem_object_unpin_map(out);
+out_out:
+ i915_gem_object_put(out);
+out_act:
+ i915_gem_object_put(act);
+out_bbe:
+ i915_gem_object_put(bbe);
+out_unlock:
+ mutex_unlock(&i915->drm.struct_mutex);
+ mock_file_free(i915, file);
+ return err;
+}
+
int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
@@ -1722,6 +1963,7 @@ int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_ggtt_pot),
SUBTEST(igt_ggtt_fill),
SUBTEST(igt_ggtt_page),
+ SUBTEST(igt_cs_tlb),
};
GEM_BUG_ON(offset_in_page(i915->ggtt.vm.total));
--
2.23.0
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