[PATCH] drm/i915: Delegate our irq handler to a thread

Chris Wilson chris at chris-wilson.co.uk
Thu Sep 26 19:54:46 UTC 2019


Moving our primary irq handler to a RT thread incurs an extra 1us delay
in processing interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency to the client. It also imposes a
delay in feeding the GPU, an extra 1us before signaling secondary engines
and extra latency in resubmitting work to keep the GPU busy. The latter
case is insignificant as the latency hidden by the active GPU, and
preempt-to-busy ensures that no extra latency is incurred for
preemption.

The benefit is that we reduce the impact on the rest of the system,
gem_syslatency [cyclictest] shows a reduction from 5us mean latency to
2us, with the maximum observed latency (in a 2 minute window) reduced by
over 160us.

v2: Only convert MSI EDGE interrupt handlers over to threaded irq. The
older LEVEL interrupts will need a manual primary handler to convert the
irq into an EDGE with IRQF_ONESHOT before handing over to the thread.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Clark Williams <williams at redhat.com>
Cc: Sebastian Andrzej Siewior <bigeasy at linutronix.de>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 --
 drivers/gpu/drm/i915/i915_irq.c           | 16 ++++++++++++----
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f451d5076bde..6d85306d5afc 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1058,8 +1058,6 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
 	if (execlists_active(&engine->execlists)) {
 		struct tasklet_struct *t = &engine->execlists.tasklet;
 
-		synchronize_hardirq(engine->i915->drm.pdev->irq);
-
 		local_bh_disable();
 		if (tasklet_trylock(t)) {
 			/* Must wait for any GPU reset in progress. */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bc83f094065a..81a2f57e9201 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1661,13 +1661,15 @@ void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 	struct intel_gt *gt = &dev_priv->gt;
 
 	if (pm_iir & dev_priv->pm_rps_events) {
-		spin_lock(&gt->irq_lock);
+		unsigned long flags;
+
+		spin_lock_irqsave(&gt->irq_lock, flags);
 		gen6_gt_pm_mask_irq(gt, pm_iir & dev_priv->pm_rps_events);
 		if (rps->interrupts_enabled) {
 			rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
 			schedule_work(&rps->work);
 		}
-		spin_unlock(&gt->irq_lock);
+		spin_unlock_irqrestore(&gt->irq_lock, flags);
 	}
 
 	if (INTEL_GEN(dev_priv) >= 8)
@@ -4478,6 +4480,7 @@ static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
 int intel_irq_install(struct drm_i915_private *dev_priv)
 {
 	int irq = dev_priv->drm.pdev->irq;
+	irq_handler_t fn, thread_fn;
 	int ret;
 
 	/*
@@ -4491,8 +4494,13 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
 
 	intel_irq_reset(dev_priv);
 
-	ret = request_irq(irq, intel_irq_handler(dev_priv),
-			  IRQF_SHARED, DRIVER_NAME, dev_priv);
+	fn = intel_irq_handler(dev_priv);
+	thread_fn = NULL;
+	if (dev_priv->drm.pdev->msi_enabled)
+		swap(fn, thread_fn);
+
+	ret = request_threaded_irq(irq, fn, thread_fn,
+				   IRQF_SHARED, DRIVER_NAME, dev_priv);
 	if (ret < 0) {
 		dev_priv->drm.irq_enabled = false;
 		return ret;
-- 
2.23.0



More information about the Intel-gfx-trybot mailing list