[PATCH 3/4] hmmm
Chris Wilson
chris at chris-wilson.co.uk
Sat Apr 25 08:07:44 UTC 2020
---
drivers/gpu/drm/i915/gt/intel_rps.c | 19 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_rps.h | 10 ++++++++++
drivers/gpu/drm/i915/gt/intel_rps_types.h | 2 ++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 58a10b3d60ba..7ee11e79dc90 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -742,6 +742,7 @@ void intel_rps_unpark(struct intel_rps *rps)
mutex_unlock(&rps->lock);
+ rps->pm_iir = 0;
if (intel_rps_has_interrupts(rps))
rps_enable_interrupts(rps);
@@ -754,6 +755,7 @@ void intel_rps_park(struct intel_rps *rps)
if (!intel_rps_clear_active(rps))
return;
+ del_timer_sync(&rps->timer);
if (intel_rps_has_interrupts(rps))
rps_disable_interrupts(rps);
@@ -844,6 +846,9 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val));
}
+
+ if (intel_rps_uses_timer(rps) && val < rps->max_freq_softlimit)
+ mod_timer(&rps->timer, jiffies + 1);
}
rps->cur_freq = val;
@@ -1673,12 +1678,21 @@ void gen5_rps_irq_handler(struct intel_rps *rps)
spin_unlock(&mchdev_lock);
}
+static void rps_timer(struct timer_list *t)
+{
+ struct intel_rps *rps = from_timer(rps, t, timer);
+
+ rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;
+ schedule_work(&rps->work);
+}
+
void intel_rps_init_early(struct intel_rps *rps)
{
mutex_init(&rps->lock);
mutex_init(&rps->power.mutex);
INIT_WORK(&rps->work, rps_work);
+ timer_setup(&rps->timer, rps_timer, 0);
atomic_set(&rps->num_waiters, 0);
}
@@ -1738,7 +1752,10 @@ void intel_rps_init(struct intel_rps *rps)
if (INTEL_GEN(i915) >= 6) {
rps_disable_interrupts(rps);
- intel_rps_set_interrupts(rps);
+ if (HAS_EXECLISTS(i915))
+ intel_rps_set_timer(rps);
+ else
+ intel_rps_set_interrupts(rps);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 8276c4e9d78f..31c2604bcf16 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -76,4 +76,14 @@ static inline void intel_rps_set_interrupts(struct intel_rps *rps)
set_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
}
+static inline bool intel_rps_uses_timer(const struct intel_rps *rps)
+{
+ return test_bit(INTEL_RPS_TIMER, &rps->flags);
+}
+
+static inline void intel_rps_set_timer(struct intel_rps *rps)
+{
+ set_bit(INTEL_RPS_TIMER, &rps->flags);
+}
+
#endif /* INTEL_RPS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h b/drivers/gpu/drm/i915/gt/intel_rps_types.h
index 624e93108da4..0ae0e784dbfe 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps_types.h
@@ -35,6 +35,7 @@ enum {
INTEL_RPS_ENABLED = 0,
INTEL_RPS_ACTIVE,
INTEL_RPS_INTERRUPTS,
+ INTEL_RPS_TIMER,
};
struct intel_rps {
@@ -44,6 +45,7 @@ struct intel_rps {
* work, interrupts_enabled and pm_iir are protected by
* dev_priv->irq_lock
*/
+ struct timer_list timer;
struct work_struct work;
unsigned long flags;
u32 pm_iir;
--
2.20.1
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