[PATCH] drm/i915: Experimental w/a for TGL according to BSpec

[Stanislav Lisovskiy]

For FBC enabling we need to wait for one vblank between
plane 1A enable and enabling the FBC.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db2a5a1a9b35..d74cd8243dfe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6507,6 +6507,9 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
 		hsw_enable_ips(new_crtc_state);
 
+	if (IS_TIGERLAKE(dev_priv))
+		intel_wait_for_vblank(dev_priv, pipe);
+
 	intel_fbc_post_update(state, crtc);
 
 	if (needs_nv12_wa(old_crtc_state) &&
-- 
2.24.1.485.gad05a3d8e5