[PATCH] drm/i915/display: Enable KBL WA 1142

[Uma Shankar]

It seems KBL WA 1142 is applicable for TGl as well.
Underruns found with FBC, but also could impact cases without FBC.
WA: Before enabling display planes or cursor, program 0x42084 bits
14:13=10b and 0x42080 bit 22=1b. Keep this value while planes or
cursor are enabled. The value is ignored while planes and cursor
are all disabled. The same programming is used with and without FBC.

Signed-off-by: Uma Shankar <uma.shankar at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dca7665c0fd..de1085556132 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7870,6 +7870,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
 
 #define CHICKEN_PAR1_1			_MMIO(0x42080)
+#define  TGL_SPARE_22			(1 << 22)
 #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
 #define  DPA_MASK_VBLANK_SRD		(1 << 15)
 #define  FORCE_ARB_IDLE_PLANES		(1 << 14)
@@ -7881,6 +7882,8 @@ enum {
 
 #define CHICKEN_MISC_2		_MMIO(0x42084)
 #define  CNL_COMP_PWR_DOWN	(1 << 23)
+#define  TGL_SPARE_14		(1 << 14)
+#define  TGL_SPARE_13		(1 << 13)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL0_PWR_DOWN	(1 << 10)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfabbe0481ab..e7fb6c77447f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7125,7 +7125,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 vd_pg_enable = 0;
-	unsigned int i;
+	unsigned int i, val;
 
 	/* Wa_1409120013:tgl */
 	I915_WRITE(ILK_DPFC_CHICKEN,
@@ -7149,6 +7149,15 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 	/* Wa_14011059788:tgl */
 	intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
 			 0, DFR_DISABLE);
+
+	/* Wa_Kbl_1142 */
+	val = I915_READ(CHICKEN_MISC_2);
+	val &= ~TGL_SPARE_13;
+	val |= TGL_SPARE_14;
+	I915_WRITE(CHICKEN_MISC_2, val);
+
+	I915_WRITE(CHICKEN_PAR1_1,
+		   I915_READ(CHICKEN_PAR1_1) | TGL_SPARE_22);
 }
 
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.22.0