[PATCH] drm/i915/gt: Rejig "Forcibly evict stable csb entries" for Tigerlake

[Chris Wilson]

It appears the timings on Tigerlake have very slightly changed,
rendering our workaround for the Global Observability Point problem on
Icelake ineffective. Let's try applying the clflush at the point of
reading from the CSB.

Suggested-by: Bruce Chang <yu.bruce.chang at intel.com>
References: https://gitlab.freedesktop.org/drm/intel/-/issues/2045
References: d8f505311717 ("drm/i915/icl: Forcibly evict stale csb entries")
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Bruce Chang <yu.bruce.chang at intel.com>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 417f6b0c6c61..1349450e791f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2470,6 +2470,15 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 	clflush((void *)last);
 }
 
+static inline u64 gen12_csb_entry(const u32 *csb)
+{
+	mb();
+	clflush((void *)csb);
+	mb();
+
+	return *(volatile u64 *)csb;
+}
+
 /*
  * Starting with Gen12, the status has a new format:
  *
@@ -2499,11 +2508,11 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 static inline bool
 gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
 {
-	u32 lower_dw = csb[0];
-	u32 upper_dw = csb[1];
-	bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_dw);
-	bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_dw);
-	bool new_queue = lower_dw & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
+	u64 entry = gen12_csb_entry(csb);
+	bool ctx_to_valid = GEN12_CSB_CTX_VALID(lower_32_bits(entry));
+	bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(entry));
+	bool new_queue =
+		lower_32_bits(entry) & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
 
 	/*
 	 * The context switch detail is not guaranteed to be 5 when a preemption
@@ -2522,7 +2531,7 @@ gen12_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
 	 * context switch on an unsuccessful wait instruction since we always
 	 * use polling mode.
 	 */
-	GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_dw));
+	GEM_BUG_ON(GEN12_CTX_SWITCH_DETAIL(upper_32_bits(entry)));
 	return false;
 }
 
-- 
2.20.1