[PATCH 2/3] drm/i915/dsb: multi dsb instance support in dsb-write()
Animesh Manna
animesh.manna at intel.com
Mon Aug 10 13:33:37 UTC 2020
Signed-off-by: Animesh Manna <animesh.manna at intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 40 +++++++++++++---------
drivers/gpu/drm/i915/display/intel_dsb.c | 8 ++---
drivers/gpu/drm/i915/display/intel_dsb.h | 4 +--
3 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 945bb03bdd4d..cdd0b5ca0ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -721,9 +721,12 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16,
+ DSB1);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -732,11 +735,11 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
- 1 << 16);
+ 1 << 16, DSB1);
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
- 1 << 16);
+ 1 << 16, DSB1);
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
- 1 << 16);
+ 1 << 16, DSB1);
}
}
@@ -901,9 +904,12 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
enum pipe pipe = crtc->pipe;
/* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue,
+ DSB1);
}
static void
@@ -923,15 +929,15 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
* 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
*/
intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
- PAL_PREC_AUTO_INCREMENT);
+ PAL_PREC_AUTO_INCREMENT, DSB1);
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = &lut[i];
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
+ ilk_lut_12p4_ldw(entry), DSB1);
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ ilk_lut_12p4_udw(entry), DSB1);
}
}
@@ -956,13 +962,13 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
* seg2[0] being unused by the hardware.
*/
intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe),
- PAL_PREC_AUTO_INCREMENT);
+ PAL_PREC_AUTO_INCREMENT, DSB1);
for (i = 1; i < 257; i++) {
entry = &lut[i * 8];
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
+ ilk_lut_12p4_ldw(entry), DSB1);
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ ilk_lut_12p4_udw(entry), DSB1);
}
/*
@@ -980,9 +986,9 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
for (i = 0; i < 256; i++) {
entry = &lut[i * 8 * 128];
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
+ ilk_lut_12p4_ldw(entry), DSB1);
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ ilk_lut_12p4_udw(entry), DSB1);
}
/* The last entry in the LUT is to be programmed in GCMAX */
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index cef1015cc04f..c968c9785484 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -90,9 +90,9 @@ static bool intel_dsb_disable_engine(struct drm_i915_private *i915,
*/
void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
- i915_reg_t reg, u32 val)
+ i915_reg_t reg, u32 val, enum dsb_id id)
{
- struct intel_dsb *dsb = crtc_state->dsb[0];
+ struct intel_dsb *dsb = crtc_state->dsb[id];
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf;
@@ -167,14 +167,14 @@ void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
* through mmio write.
*/
void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
- i915_reg_t reg, u32 val)
+ i915_reg_t reg, u32 val, enum dsb_id id)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_dsb *dsb;
u32 *buf;
- dsb = crtc_state->dsb[0];
+ dsb = crtc_state->dsb[id];
if (!dsb) {
intel_de_write(dev_priv, reg, val);
return;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 654a11f24b80..0040941d6a56 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -43,9 +43,9 @@ struct intel_dsb {
void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
- i915_reg_t reg, u32 val);
+ i915_reg_t reg, u32 val, enum dsb_id id);
void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
- i915_reg_t reg, u32 val);
+ i915_reg_t reg, u32 val, enum dsb_id id);
void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
#endif
--
2.26.0
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