[PATCH 2/2] icl-fixup?
Chris Wilson
chris at chris-wilson.co.uk
Tue Aug 11 08:08:11 UTC 2020
---
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 3f7a8aae55aa..16bb74625957 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -57,8 +57,7 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine)
u32 offset = i915_ggtt_offset(engine->status_page.vma);
struct intel_context *ce;
struct i915_request *rq;
- u32 d_ring, d_ctx;
- u64 start, end;
+ u64 d_ring, d_ctx, dt;
u32 *cs;
ce = intel_context_create(engine);
@@ -100,11 +99,11 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine)
/* Run the request for a 100us, sampling timestamps before/after */
preempt_disable();
- start = ktime_get_mono_fast_ns();
+ dt = ktime_get_mono_fast_ns();
write_semaphore(&sema[2], 0);
udelay(100);
write_semaphore(&sema[2], 1);
- end = ktime_get_mono_fast_ns();
+ dt = ktime_get_mono_fast_ns() - dt;
preempt_enable();
if (i915_request_wait(rq, 0, HZ / 2) < 0) {
@@ -122,10 +121,16 @@ static int __live_engine_timestamps(struct intel_engine_cs *engine)
d_ring = sema[4] - sema[0];
pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n",
- engine->name, end - start,
+ engine->name, dt,
intel_gt_clock_interval_to_ns(engine->gt, d_ctx),
intel_gt_clock_interval_to_ns(engine->gt, d_ring));
+ d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz;
+ if (INTEL_GEN(engine->i915) == 11)
+ d_ring *= 12500000; /* Fixed 80ns for icl ctx? */
+ else
+ d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz;
+
if (4 * d_ctx > 5 * d_ring || 5 * d_ctx < 4 * d_ring) {
pr_err("%s Mismatch between ring and context timestamps!\n",
engine->name);
--
2.20.1
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