[PATCH] drm/i915: Check if dsabling SAGV and possibly some C States, helps against periodical exceeding pipe update time, apparently caused my mmios ocassionally taking longer than expected.

[Stanislav Lisovskiy]

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b4bd19266b8c..af2a93d6ab3a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3953,6 +3953,8 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state)
 {
+	return false;
+
 	if (INTEL_GEN(dev_priv) < 11 &&
 	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
 		return false;
@@ -5007,6 +5009,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
 				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
 
+			if (level > 0)
+				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+
 			/*
 			 * Wa_1408961008:icl, ehl
 			 * Underruns with WM1+ disabled
-- 
2.24.1.485.gad05a3d8e5