[PATCH 2/2] debug

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index a4b8aa6d0a9e..9acbb5313de2 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -388,16 +388,22 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 
 skip_phy_misc:
 		if (INTEL_GEN(dev_priv) >= 12) {
+			u32 val2;
+
 			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
 			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
 			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
 			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
 			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
+			val2 = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
+			drm_info(&dev_priv->drm, "ICL_PORT_TX_DW8_GRP expected=0x%x read=0x%x\n", val, val2);
 
 			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
 			val &= ~DCC_MODE_SELECT_MASK;
 			val |= DCC_MODE_SELECT_CONTINUOSLY;
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
+			val2 = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
+			drm_info(&dev_priv->drm, "ICL_PORT_PCS_DW1_GRP expected=0x%x read=0x%x\n", val, val2);
 		}
 
 		cnl_set_procmon_ref_values(dev_priv, phy);
-- 
2.28.0