[PATCH 10/11] drm/i915: Add intel_update_bigjoiner handling.
Maarten Lankhorst
maarten.lankhorst at linux.intel.com
Wed Feb 5 10:05:44 UTC 2020
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used,
so use the vblank evasion to cover both pipes.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 127 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 25 +++-
drivers/gpu/drm/i915/display/intel_sprite.h | 3 +-
3 files changed, 131 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f979c3293116..961a069fad5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15695,7 +15695,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
else
i9xx_update_planes_on_crtc(state, crtc);
- intel_pipe_update_end(new_crtc_state);
+ intel_pipe_update_end(new_crtc_state, NULL);
/*
* We usually enable FIFO underrun interrupts as part of the
@@ -15804,6 +15804,54 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
}
}
+static void intel_update_bigjoiner(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ bool modeset = needs_modeset(new_crtc_state);
+ struct intel_crtc *slave = new_crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ if (modeset) {
+ /* Enable slave first */
+ intel_crtc_update_active_timings(new_slave_crtc_state);
+ dev_priv->display.crtc_enable(state, slave);
+
+ /* Then master */
+ intel_crtc_update_active_timings(new_crtc_state);
+ dev_priv->display.crtc_enable(state, crtc);
+
+ /* vblanks work again, re-enable pipe CRC. */
+ intel_crtc_enable_pipe_crc(crtc);
+
+ } else {
+ intel_pre_plane_update(state, crtc);
+ intel_pre_plane_update(state, slave);
+
+ if (new_crtc_state->update_pipe)
+ intel_encoders_update_pipe(state, crtc);
+ }
+
+ /*
+ * Perform vblank evasion around commit operation, and make sure to
+ * commit both planes simultaneously for best results.
+ */
+ intel_pipe_update_start(new_crtc_state);
+
+ commit_pipe_config(state, old_crtc_state, new_crtc_state);
+ commit_pipe_config(state, old_slave_crtc_state, new_slave_crtc_state);
+
+ skl_update_planes_on_crtc(state, crtc);
+ skl_update_planes_on_crtc(state, slave);
+
+ intel_pipe_update_end(new_crtc_state, new_slave_crtc_state);
+}
+
static void intel_commit_modeset_enables(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
@@ -15868,7 +15916,7 @@ static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
intel_pipe_update_start(new_crtc_state);
commit_pipe_config(state, old_crtc_state, new_crtc_state);
skl_update_planes_on_crtc(state, crtc);
- intel_pipe_update_end(new_crtc_state);
+ intel_pipe_update_end(new_crtc_state, NULL);
/*
* We usually enable FIFO underrun interrupts as part of the
@@ -15932,18 +15980,25 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc *crtc;
+ struct intel_crtc *crtc, *slave;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
u8 required_slices = state->wm_results.ddb.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
+ struct skl_ddb_entry new_entries[I915_MAX_PIPES] = {};
const u8 num_pipes = INTEL_NUM_PIPES(dev_priv);
+ const struct intel_crtc_state *slave_crtc_state;
u8 update_pipes = 0, modeset_pipes = 0;
int i;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
+ if (new_crtc_state->bigjoiner_slave) {
+ /* We're updated from master */
+ continue;
+ }
+
if (!new_crtc_state->hw.active)
continue;
@@ -15954,6 +16009,34 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
} else {
modeset_pipes |= BIT(pipe);
}
+
+ if (new_crtc_state->bigjoiner) {
+ slave = new_crtc_state->bigjoiner_linked_crtc;
+ slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state,
+ slave);
+
+ /* put both entries in */
+ new_entries[i].start = new_crtc_state->wm.skl.ddb.start;
+ new_entries[i].end = slave_crtc_state->wm.skl.ddb.end;
+ } else {
+ new_entries[i] = new_crtc_state->wm.skl.ddb;
+ }
+
+ /* ignore allocations for crtc's that have been turned off during modeset. */
+ if (needs_modeset(new_crtc_state))
+ continue;
+
+ if (old_crtc_state->bigjoiner) {
+ slave = old_crtc_state->bigjoiner_linked_crtc;
+ slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ entries[i].start = old_crtc_state->wm.skl.ddb.start;
+ entries[i].end = slave_crtc_state->wm.skl.ddb.end;
+ } else {
+ entries[i] = old_crtc_state->wm.skl.ddb;
+ }
}
/* If 2nd DBuf slice required, enable it here */
@@ -15973,29 +16056,36 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
+ bool ddb_changed;
if ((update_pipes & BIT(pipe)) == 0)
continue;
- if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ if (skl_ddb_allocation_overlaps(&new_entries[pipe],
entries, num_pipes, pipe))
continue;
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ ddb_changed = !skl_ddb_entry_equal(&new_entries[pipe], &entries[pipe]);
+ entries[pipe] = new_entries[pipe];
update_pipes &= ~BIT(pipe);
- intel_update_crtc(crtc, state, old_crtc_state,
- new_crtc_state);
-
/*
* If this is an already active pipe, it's DDB changed,
* and this isn't the last pipe that needs updating
* then we need to wait for a vblank to pass for the
* new ddb allocation to take effect.
*/
- if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
- &old_crtc_state->wm.skl.ddb) &&
- (update_pipes | modeset_pipes))
+
+ if (new_crtc_state->bigjoiner) {
+ intel_update_bigjoiner(crtc, state,
+ old_crtc_state,
+ new_crtc_state);
+ } else {
+ intel_update_crtc(crtc, state, old_crtc_state,
+ new_crtc_state);
+ }
+
+ if (ddb_changed && (update_pipes | modeset_pipes))
intel_wait_for_vblank(dev_priv, pipe);
}
}
@@ -16015,10 +16105,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
is_trans_port_sync_slave(new_crtc_state))
continue;
- WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ WARN_ON(skl_ddb_allocation_overlaps(&new_entries[pipe],
entries, num_pipes, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_entries[pipe];
modeset_pipes &= ~BIT(pipe);
if (is_trans_port_sync_mode(new_crtc_state)) {
@@ -16029,9 +16119,12 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
new_crtc_state);
slave_crtc = intel_get_slave_crtc(new_crtc_state);
- /* TODO: update entries[] of slave */
modeset_pipes &= ~BIT(slave_crtc->pipe);
-
+ entries[slave_crtc->pipe] = new_entries[slave_crtc->pipe];
+ } else if (new_crtc_state->bigjoiner) {
+ intel_update_bigjoiner(crtc, state,
+ old_crtc_state,
+ new_crtc_state);
} else {
intel_update_crtc(crtc, state, old_crtc_state,
new_crtc_state);
@@ -16050,10 +16143,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if ((modeset_pipes & BIT(pipe)) == 0)
continue;
- WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ WARN_ON(skl_ddb_allocation_overlaps(&new_entries[pipe],
entries, num_pipes, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_entries[pipe];
modeset_pipes &= ~BIT(pipe);
intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 60613fb00f93..2a41893e38f3 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -98,6 +98,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
/* FIXME needs to be calibrated sensibly */
min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ new_crtc_state->bigjoiner ?
+ 2 * VBLANK_EVASION_TIME_US :
VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
@@ -190,7 +192,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
* re-enables interrupts and verifies the update was actually completed
* before a vblank.
*/
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state,
+ struct intel_crtc_state *slave_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
@@ -205,16 +208,26 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
* while ... */
- if (new_crtc_state->uapi.event) {
- drm_WARN_ON(&dev_priv->drm,
- drm_crtc_vblank_get(&crtc->base) != 0);
+ if (new_crtc_state->uapi.event || (slave_crtc_state && slave_crtc_state->uapi.event)) {
+ if (new_crtc_state->uapi.event)
+ drm_WARN_ON(&dev_priv->drm,
+ drm_crtc_vblank_get(&crtc->base) != 0);
+ if (slave_crtc_state && slave_crtc_state->uapi.event)
+ drm_WARN_ON(&dev_priv->drm,
+ drm_crtc_vblank_get(&crtc->base) != 0);
spin_lock(&crtc->base.dev->event_lock);
- drm_crtc_arm_vblank_event(&crtc->base,
- new_crtc_state->uapi.event);
+ if (new_crtc_state->uapi.event)
+ drm_crtc_arm_vblank_event(&crtc->base,
+ new_crtc_state->uapi.event);
+ if (slave_crtc_state && slave_crtc_state->uapi.event)
+ drm_crtc_arm_vblank_event(&crtc->base,
+ slave_crtc_state->uapi.event);
spin_unlock(&crtc->base.dev->event_lock);
new_crtc_state->uapi.event = NULL;
+ if (slave_crtc_state)
+ slave_crtc_state->uapi.event = NULL;
}
local_irq_enable();
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
index 5eeaa92420d1..31335d12cf56 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -24,7 +24,8 @@ struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state,
+ struct intel_crtc_state *slave_crtc_state);
int intel_plane_check_stride(const struct intel_plane_state *plane_state);
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
--
2.25.0.24.g3f081b084b0
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