[PATCH 07/12] drm/i915/gt: Avoid mmio reads when setting up interrupts from idle

Chris Wilson chris at chris-wilson.co.uk
Sun Jan 5 23:58:35 UTC 2020


If we know the submission engine is idle, we do not need to post the
write to enable interrupts as they will be enabled prior to submission.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 28c05e7a1510..bf9bea378148 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3446,12 +3446,13 @@ static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
 {
 	ENGINE_WRITE(engine, RING_IMR,
 		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
-	ENGINE_POSTING_READ(engine, RING_IMR);
+	if (execlists_active(&engine->execlists))
+		ENGINE_POSTING_READ(engine, RING_IMR);
 }
 
 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
 {
-	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
+	ENGINE_WRITE_FW(engine, RING_IMR, ~engine->irq_keep_mask);
 }
 
 static int gen8_emit_flush(struct i915_request *request, u32 mode)
-- 
2.25.0.rc1



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