[RFC 3/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Thu Jan 9 16:54:25 UTC 2020
From: Ankit Navik <ankit.p.navik at intel.com>
This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select optimum configuration from
pre-defined optimum configuration table(opt_config).
It also introduce flag update_render_config which can set by any governor.
v2:
* Move static optimum_config to device init time.
* Rename function to appropriate name, fix data types and patch ordering.
* Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)
v3:
* Add safe guard check in i915_gem_context_set_load_type.
* Rename struct from optimum_config to i915_sseu_optimum_config to
avoid namespace clashes.
* Reduces memcpy for space efficient.
* Rebase.
* Improved commit message. (Tvrtko Ursulin)
v4:
* Move optimum config table to file scope. (Tvrtko Ursulin)
v5:
* Adds optimal table of slice/sub-slice/EU for Gen 9 GT1.
* Rebase.
v6:
* Rebase.
* Fix warnings.
v7:
* Fix return conditions.
* Remove i915_gem_context_set_load_type and move logic to
__execlists_update_reg_state. (Tvrtko Ursulin)
Tvrtko Ursulin:
v8:
* Simplified and mashed up - TODO
Cc: Vipin Anand <vipin.anand at intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik at intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
.../gpu/drm/i915/gem/i915_gem_context_types.h | 13 +++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 46 +++++++++++++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 4 ++
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_sysfs.c | 34 +++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 57 ++++++++++++++++++-
7 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index a05709122cb7..ac85ae188c42 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -40,6 +40,19 @@ struct i915_gem_engines_iter {
const struct i915_gem_engines *engines;
};
+enum gem_load_type {
+ LOAD_TYPE_LOW,
+ LOAD_TYPE_MEDIUM,
+ LOAD_TYPE_HIGH,
+ LOAD_TYPE_LAST
+};
+
+struct i915_sseu_optimum_config {
+ u8 slice;
+ u8 subslice;
+ u8 eu;
+};
+
/**
* struct i915_gem_context - client state
*
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index be88d5ed23b2..aa690b04d672 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2565,8 +2565,11 @@ __execlists_update_reg_state(const struct intel_context *ce,
/* RPCS */
if (engine->class == RENDER_CLASS) {
+ struct intel_sseu dsseu;
+
regs[CTX_R_PWR_CLK_STATE] =
- intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+ intel_sseu_make_rpcs(engine->i915,
+ intel_sseu_make(&dsseu, ce));
i915_oa_init_reg_state(ce, engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 74f793423231..dbced4197576 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -4,6 +4,8 @@
* Copyright © 2019 Intel Corporation
*/
+#include "gt/intel_context_types.h"
+
#include "i915_drv.h"
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
@@ -192,3 +194,47 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
return rpcs;
}
+
+const struct intel_sseu *
+intel_sseu_make(struct intel_sseu *sseu, const struct intel_context *ce)
+{
+ const struct i915_sseu_optimum_config *cfg;
+ struct i915_gem_context *ctx;
+ enum gem_load_type load_type;
+ int freq;
+
+ GEM_BUG_ON(ce->engine->class != RENDER_CLASS);
+
+ ctx = rcu_dereference_protected(ce->gem_context, true);
+ if (!ctx || !ctx->i915->predictive_load_enable || ce->user_sseu)
+ return &ce->sseu;
+
+ freq = ctx->rq_retire_freq[ce->engine->class];
+
+ if (freq > 20) // finger in the air thresholds
+ load_type = LOAD_TYPE_HIGH;
+ else if (freq < 5)
+ load_type = LOAD_TYPE_LOW;
+ else
+ load_type = LOAD_TYPE_MEDIUM;
+
+ cfg = &ctx->i915->opt_config[load_type];
+
+ sseu->slice_mask = ~(~0UL << cfg->slice);
+ sseu->subslice_mask = ~(~0UL << cfg->subslice);
+ sseu->min_eus_per_subslice = cfg->eu;
+ sseu->max_eus_per_subslice = cfg->eu;
+
+#if 0
+ printk("dyn_sseu: %p freq=%d load_type=%u sseu=%x/%x/%u-%u [%s]\n",
+ ce,
+ freq,
+ load_type,
+ sseu->slice_mask, sseu->subslice_mask,
+ sseu->min_eus_per_subslice,
+ sseu->max_eus_per_subslice,
+ ctx->name);
+#endif
+
+ return sseu;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index d1d225204f09..16ffaa79c088 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -13,6 +13,7 @@
#include "i915_gem.h"
struct drm_i915_private;
+struct intel_context;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
@@ -97,4 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
+const struct intel_sseu *
+intel_sseu_make(struct intel_sseu *sseu, const struct intel_context *ce);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 50181113dd2b..f6a1b2d2d558 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -996,6 +996,11 @@ struct drm_i915_private {
/* protects panel power sequencer state */
struct mutex pps_mutex;
+ /* optimal slice/subslice/EU configration state */
+ const struct i915_sseu_optimum_config *opt_config;
+
+ bool predictive_load_enable;
+
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
unsigned int max_cdclk_freq;
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index ad2b1b833d7b..12dce6f92f68 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -432,12 +432,45 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
return ret ?: count;
}
+static ssize_t deu_enable_show(struct device *kdev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", i915->predictive_load_enable);
+}
+
+static ssize_t deu_enable_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
+ ssize_t ret;
+ u32 val;
+
+ ret = kstrtou32(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ /* Check invalid values */
+ if (val != 0 && val != 1)
+ return -EINVAL;
+
+ i915->predictive_load_enable = val;
+
+ return count;
+}
+
static DEVICE_ATTR_RO(gt_act_freq_mhz);
static DEVICE_ATTR_RO(gt_cur_freq_mhz);
static DEVICE_ATTR_RW(gt_boost_freq_mhz);
static DEVICE_ATTR_RW(gt_max_freq_mhz);
static DEVICE_ATTR_RW(gt_min_freq_mhz);
+static DEVICE_ATTR_RW(deu_enable);
+
static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
@@ -473,6 +506,7 @@ static const struct attribute * const gen6_attrs[] = {
&dev_attr_gt_RP0_freq_mhz.attr,
&dev_attr_gt_RP1_freq_mhz.attr,
&dev_attr_gt_RPn_freq_mhz.attr,
+ &dev_attr_deu_enable.attr,
NULL,
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6670a0763be2..769567f0379d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -896,6 +896,34 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}
+/* static table of slice/subslice/EU for Cherryview */
+static const struct i915_sseu_optimum_config chv_config[LOAD_TYPE_LAST] = {
+ {1, 1, 4}, /* Low */
+ {1, 1, 6}, /* Medium */
+ {1, 2, 6} /* High */
+};
+
+/* static table of slice/subslice/EU for GLK GT1 */
+static const struct i915_sseu_optimum_config glk_gt1_config[LOAD_TYPE_LAST] = {
+ {1, 2, 2}, /* Low */
+ {1, 2, 3}, /* Medium */
+ {1, 2, 6} /* High */
+};
+
+/* static table of slice/subslice/EU for KBL GT2 */
+static const struct i915_sseu_optimum_config kbl_gt2_config[LOAD_TYPE_LAST] = {
+ {1, 3, 2}, /* Low */
+ {1, 3, 4}, /* Medium */
+ {1, 3, 8} /* High */
+};
+
+/* static table of slice/subslice/EU for KBL GT3 */
+static const struct i915_sseu_optimum_config kbl_gt3_config[LOAD_TYPE_LAST] = {
+ {2, 3, 4}, /* Low */
+ {2, 3, 6}, /* Medium */
+ {2, 3, 8} /* High */
+};
+
/**
* intel_device_info_runtime_init - initialize runtime info
* @dev_priv: the i915 device
@@ -1022,12 +1050,37 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
/* Initialize slice/subslice/EU info */
if (IS_HASWELL(dev_priv))
hsw_sseu_info_init(dev_priv);
- else if (IS_CHERRYVIEW(dev_priv))
+ else if (IS_CHERRYVIEW(dev_priv)) {
cherryview_sseu_info_init(dev_priv);
+ BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
+ dev_priv->opt_config = chv_config;
+ }
else if (IS_BROADWELL(dev_priv))
bdw_sseu_info_init(dev_priv);
- else if (IS_GEN(dev_priv, 9))
+ else if (IS_GEN(dev_priv, 9)) {
gen9_sseu_info_init(dev_priv);
+
+ // FIXME tursulin: are the glk/kbl tables supposed to apply to all Gen9?
+
+ switch (info->gt) {
+ default: /* fall through */
+ case 1:
+ BUILD_BUG_ON(ARRAY_SIZE(glk_gt1_config) !=
+ LOAD_TYPE_LAST);
+ dev_priv->opt_config = glk_gt1_config;
+ break;
+ case 2:
+ BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config) !=
+ LOAD_TYPE_LAST);
+ dev_priv->opt_config = kbl_gt2_config;
+ break;
+ case 3:
+ BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config) !=
+ LOAD_TYPE_LAST);
+ dev_priv->opt_config = kbl_gt3_config;
+ break;
+ }
+ }
else if (IS_GEN(dev_priv, 10))
gen10_sseu_info_init(dev_priv);
else if (IS_GEN(dev_priv, 11))
--
2.20.1
More information about the Intel-gfx-trybot
mailing list