[PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers

[José Roberto de Souza]

From: Radhakrishna Sripada <radhakrishna.sripada at intel.com>

dgfx platforms do not support CPU fence and FBC host tracking so
lets avoid write to removed registers.

Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Cc: Matt Roper <matthew.d.roper at intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1587bd804b48..0b0e3ca43b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -312,7 +312,12 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 		break;
 	}
 
-	if (params->fence_id >= 0) {
+	if (IS_DGFX(dev_priv)) {
+		/*
+		 * dGFX GPUs don't have apperture/fences and only rely on FBC
+		 * render nuke to track frontbuffer modifications
+		 */
+	} else if (params->fence_id >= 0) {
 		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 		I915_WRITE(SNB_DPFC_CTL_SA,
 			   SNB_CPU_FENCE_ENABLE |
-- 
2.25.0