[PATCH v14 3/6] drm/i915: Refactor intel_can_enable_sagv
Stanislav Lisovskiy
stanislav.lisovskiy at intel.com
Tue Jan 28 16:14:58 UTC 2020
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
calls when copying level 0 water marks for enabled SAGV, to
fix this now simply using that field right away, without copying,
for that introduced a new wm_level accessor which decides which
wm_level to return based on SAGV state.
v8: - Protect crtc_sagv_mask same way as we do for other global state
changes: i.e check if changes are needed, then grab all crtc locks
to serialize the changes(Ville Syrjälä)
- Add crtc_sagv_mask caching in order to avoid needless recalculations
(Matthew Roper)
- Put back Gen12 SAGV switch in order to get it enabled in separate
patch(Matthew Roper)
- Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper)
- Check if there are no active pipes in intel_can_enable_sagv
instead of platform specific functions(Matthew Roper), same
for intel_has_sagv check.
v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä)
- crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä)
- Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask
- Extracted skl_plane_wm_level function and passing latency to
separate patches(Ville Syrjälä)
- Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm
(Ville Syrjälä)
- Now using simple assignment for sagv_wm0 as it contains only
pod types and no pointers(Ville Syrjälä)
- Fixed intel_can_enable_sagv not to do double duty, now it only
check SAGV bits by ANDing those between local and global state.
The SAGV masks are now computed after watermarks are available,
in order to be able to figure out if ddb ranges are fitting nicely.
(Ville Syrjälä)
- Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic
when using skl_plane_wm_level accessor, as we had previously for Gen11+
color plane and regular wm levels, so probably both has to be recalculated
with additional SAGV block time for Level 0.
- (Temporary) Added dump stack in order to figure out when we get 0 state
for skl_plane_wm_level accessor, most likely this happens at the commit
stage when state is already zeroed out.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
Cc: Ville Syrjälä <ville.syrjala at intel.com>
Cc: James Ausmus <james.ausmus at intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../drm/i915/display/intel_display_types.h | 15 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_pm.c | 326 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 1 +
5 files changed, 330 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 79f9054078ea..a462709b1316 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13785,7 +13785,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
@@ -13837,7 +13840,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0) &&
+ (level == 0)))
continue;
DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
@@ -15418,6 +15424,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
dev_priv->display.optimize_watermarks(state, crtc);
}
+ dev_priv->pipe_sagv_mask = state->pipe_sagv_mask;
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 33ba93863488..c8a458d46a61 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -494,6 +494,19 @@ struct intel_atomic_state {
*/
u8 active_pipe_changes;
+ /*
+ * Contains a mask which reflects whether correspondent pipe
+ * can tolerate SAGV or not, so that we can make a decision
+ * at atomic_commit_tail stage, whether we enable it or not
+ * based on global state in dev_priv.
+ */
+ u8 pipe_sagv_mask;
+ /*
+ * Used to determine if we already had calculated
+ * SAGV mask for this state once.
+ */
+ bool sagv_calculated;
+
u8 active_pipes;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
@@ -674,6 +687,8 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8a08c63278e..0958c6c495bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1167,6 +1167,12 @@ struct drm_i915_private {
u32 sagv_block_time_us;
+ /*
+ * Contains a bit mask, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_mask;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5109757ced6d..829b89831193 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3675,7 +3675,7 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3798,39 +3798,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool skl_can_enable_sagv_on_pipe(struct intel_atomic_state *state,
+ enum pipe pipe)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
-
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(pipe));
return false;
+ }
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3857,7 +3842,132 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us, pipe_name(pipe));
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static void skl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ enum pipe pipe;
+
+ if (state->active_pipes != 1) {
+ state->pipe_sagv_mask = 0;
+ DRM_DEBUG_KMS("No SAGV for multiple pipes on Gen 9\n");
+ return;
+ }
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+
+ if (skl_can_enable_sagv_on_pipe(state, pipe))
+ state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+}
+
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ if (skl_can_enable_sagv_on_pipe(state, crtc->pipe))
+ state->pipe_sagv_mask |= BIT(crtc->pipe);
+ else
+ state->pipe_sagv_mask &= ~BIT(crtc->pipe);
+ }
+}
+
+void intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ /*
+ * Make sure we always pick global state first,
+ * there shouldn't be any issue as we hold only locks
+ * to correspondent crtcs in state, however once
+ * we detect that we need to change SAGV mask
+ * in global state, we will grab all the crtc locks
+ * in order to get this serialized, thus other
+ * racing commits having other crtc locks, will have
+ * to start over again, as stated by Wound-Wait
+ * algorithm.
+ */
+ state->pipe_sagv_mask = dev_priv->pipe_sagv_mask;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_compute_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_compute_sagv_mask(state);
+ else
+ skl_compute_sagv_mask(state);
+
+ state->sagv_calculated = true;
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ * Grab all locks if we detect that we are actually
+ * going to do something.
+ */
+ if (state->pipe_sagv_mask != dev_priv->pipe_sagv_mask) {
+ ret = intel_atomic_serialize_global_state(state);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return;
+ }
+ }
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int i;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+ * Should have this calculated by that time,
+ * means something got changed or wrong in the driver
+ * currently, supposed places which call this function are:
+ * intel_atomic_commit_tail, intel_atomic_bw_check,
+ * skl_allocate_pipe_ddb, skl_write_plane_wm.
+ * All of those are supposed to be called after
+ * skl_compute_wm->intel_compute_sagv_mask is called.
+ */
+ drm_WARN_ON(&dev_priv->drm, !state->sagv_calculated);
+
+ /*
+ * If there are no active CRTCs, no additional
+ * checks need be performed
+ */
+ if (hweight8(state->active_pipes) == 0)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ u32 mask = BIT(crtc->pipe);
+ bool state_sagv_masked = (mask & state->pipe_sagv_mask) == 0;
+
+ if (!new_crtc_state->hw.active)
+ continue;
+
+ if (state_sagv_masked)
return false;
}
@@ -4009,6 +4119,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
u32 latency = dev_priv->wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4279,12 +4390,85 @@ skl_plane_wm_level(struct intel_plane *plane,
int level,
int color_plane)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
+ /*
+ * Looks ridicilous but need to check if state is not
+ * NULL here as it might be as some cursor plane manipulations
+ * seem to happen when no atomic state is actually present,
+ * despite crtc_state is allocated. Removing state check
+ * from here will result in kernel panic on boot.
+ * However we now need to check whether should be use SAGV
+ * wm levels here.
+ */
+ if (state) {
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ if (intel_can_enable_sagv(intel_state) && !level)
+ return color_plane ? &wm->uv_sagv_wm0 : &wm->sagv_wm0;
+ } else
+ dump_stack();
+
return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ ddb, alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+ * The only place, where we can't use skl_plane_wm_level
+ * accessor, because if actually calls intel_can_enable_sagv
+ * which depends on that function.
+ */
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ blocks += wm->uv_sagv_wm0.min_ddb_alloc;
+
+ if (blocks > alloc_size) {
+ DRM_DEBUG_KMS("Not enough ddb blocks(%d<%d) for SAGV on pipe %c\n",
+ alloc_size, blocks, pipe_name(intel_crtc->pipe));
+ return -ENOSPC;
+ }
+ }
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
@@ -4448,7 +4632,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
/* Gen11+ uses a separate plane for UV watermarks */
drm_WARN_ON(&dev_priv->drm,
- INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
+ INTEL_GEN(dev_priv) >= 11 && uv_total[plane->id]);
/* Leave disabled planes at (0,0) */
if (total[plane->id]) {
@@ -4869,11 +5053,19 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
+ struct skl_wm_level *sagv_wm = yuv ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
@@ -4884,6 +5076,25 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
}
static u32
@@ -4976,7 +5187,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -4998,7 +5209,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5557,18 +5768,68 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+static void tgl_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ int ret;
+ int i;
+ struct intel_plane *plane;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ int pipe_bit = BIT(crtc->pipe);
+ bool skip = true;
+
+ /*
+ * If we had set this mast already once for this state,
+ * no need to waste CPU cycles for doing this again.
+ */
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+
+ if (!skl_plane_wm_equals(dev_priv,
+ &old_crtc_state->wm.skl.optimal.planes[plane_id],
+ &new_crtc_state->wm.skl.optimal.planes[plane_id])) {
+ skip = false;
+ break;
+ }
+ }
+
+ /*
+ * Check if wm levels are actually the same as for previous
+ * state, which means we can just skip doing this long check
+ * and just copy correspondent bit from previous state.
+ */
+ if (skip)
+ continue;
+
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+ if (!ret)
+ state->pipe_sagv_mask |= pipe_bit;
+ else
+ state->pipe_sagv_mask &= ~pipe_bit;
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc_state *old_crtc_state;
- struct skl_ddb_values *results = &state->wm_results;
int ret, i;
+ struct skl_ddb_values *results = &state->wm_results;
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ /* No SAGV for this state, until we check if it's possible */
+ state->pipe_sagv_mask = 0;
+
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
@@ -5595,6 +5856,12 @@ skl_compute_wm(struct intel_atomic_state *state)
results->dirty_pipes |= BIT(crtc->pipe);
}
+ /*
+ * Now once we got wm levels calculated,
+ * check if we can have SAGV.
+ */
+ intel_compute_sagv_mask(state);
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
@@ -5748,6 +6015,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
val = I915_READ(CUR_WM(pipe, level));
skl_wm_level_from_reg_val(val, &wm->wm[level]);
+ if (level == 0)
+ memcpy(&wm->sagv_wm0, &wm->wm[level],
+ sizeof(struct skl_wm_level));
}
if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index c06c6a846d9a..4136d4508e63 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.24.1.485.gad05a3d8e5
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