[PATCH 8/8] Fix the PHY pat register set sequence

[Manasi Navare]

Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++++---------
 1 file changed, 34 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3c14d2225025..c51bc2829911 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5081,20 +5081,28 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum port port = intel_dig_port->base.port;
-	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+	enum pipe pipe = crtc->pipe;
+	u32 trans_ddi_func_ctl_value, trans_conf_value;
 
-	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
-	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
 	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
+
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG: Trans DDI FUNC CTL = 0x%08x",
+		      trans_ddi_func_ctl_value);
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG: Trans CONF = 0x%08x",
+		      trans_conf_value);
 
-	ddi_buf_ctl_value        &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
-	dp_tp_ctl_value          &= ~DP_TP_CTL_ENABLE;
-	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
-				      DDI_PORT_WIDTH_MASK);
+	trans_ddi_func_ctl_value &= ~TRANS_DDI_FUNC_ENABLE;
+	trans_conf_value &= ~PIPECONF_ENABLE;
 
-	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
-	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
+	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
 	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
+
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG After disable: Trans DDI FUNC CTL = 0x%08x",
+		      I915_READ(TRANS_DDI_FUNC_CTL(port)));
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG after disable: Trans CONF = 0x%08x",
+		      intel_de_read(dev_priv, PIPECONF(pipe)));
 }
 
 static void
@@ -5104,20 +5112,28 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum port port = intel_dig_port->base.port;
-	u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
+	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+	enum pipe pipe = crtc->pipe;
+	u32 trans_ddi_func_ctl_value, trans_conf_value;
 
-	ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
-	dp_tp_ctl_value = I915_READ(TGL_DP_TP_CTL(port));
 	trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
+	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
+
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG: Trans DDI FUNC CTL = 0x%08x",
+		      trans_ddi_func_ctl_value);
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG: Trans CONF = 0x%08x",
+		      trans_conf_value);
 
-	ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH(lane_cnt);
-	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
-	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
-				    DDI_PORT_WIDTH(lane_cnt);
+	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE;
+	trans_conf_value |= PIPECONF_ENABLE;
 
 	I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
-	I915_WRITE(TGL_DP_TP_CTL(port), dp_tp_ctl_value);
-	I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
+	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
+
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG After enable: Trans DDI FUNC CTL = 0x%08x",
+		      I915_READ(TRANS_DDI_FUNC_CTL(port)));
+	DRM_DEBUG_KMS("\n DP PHY COMP DEBUG after enable: Trans CONF = 0x%08x",
+		      intel_de_read(dev_priv, PIPECONF(pipe)));
 }
 
 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
-- 
2.19.1